Modifying ARM code generator for elimination of 8bit writes - need help

[Wolfgang Mües <wolfgang at iksw-muees dot de>]

Hello,

I am trying to port big C/C++ programs (see www.dslinux.org) to the 
nintendo DS console.

The console has 4 Mbytes internal memory, and 32 MBytes external
memory which is *not* 8bit writable (only 16 and 32 bits). CPU is an ARM 
946. Using the external memory for ROM(XIP) and the internal memory for 
data, linux in console mode is possible, but graphical environments are 
very limited...

The idea to overcome this problem is to
a) activate data cache in writeback mode for the external memory.
b) modify the gcc code generator. "strb" opcode is transformed to 
"swpb". swpb will load the cache because of the read-modify-write,
and at cache writeback time, the whole cached half-line will be written 
back, eliminating the 8bit write problem. 

I have proven the solution with an assembler program, but I think I need 
some help modifying the compiler....

I found arm.md and the moveqi insns, but because of the different 
addressing modes of strb and swpb, its not easy to make the change.
And there must be a compiler option for this, too.

Could somebody please tell me how to implement this change?

regards

Wolfgang
-- 
We're back to the times when men were men 
and wrote their own device drivers.

(Linus Torvalds)