Re: GCC Port (gcc backend) for Microchip PICMicro microcontroller

[Alan Lehotsky <apl at alum dot mit dot edu>]

On Apr 11, 2006, at 03:46, Colm O' Flaherty wrote:

> I'm not quite sure I follow you.. if its possible to dedicate a  
> register to act as the data-stack pointer, and implement it that  
> way, why would I want to "keep the SP as a virtual register"?  I'm  
> not being antagonistic when I say that.. I'm just trying to  
> understand what you're trying to tell me..

Sorry, thought you were indicating that you didn't WANT a data  
stack :-)  Now I understand that your chip
just doesn't provide hardware support for stacks.

BTW, another port I did (to a RISCy architecture that was the core  
for a high-speed multiprotocol router
(never submitted to the FSF and the company's now belly-up) provides  
a "lower bound" on how simple an
addressing scheme you can deal with.

This machine had 512 directly addressable memory locations and 4  
registers that could be indirected thru
(kinda like the way the PDP-8 worked).  With 3 registers available  
for reload (1 was reserved for the SP),
you could pretty much compile all the GCC test suite that didn't need  
more than 512 words of memory.
[Oh, BTW,  chars were 32 bits on this machine also....]


> Will check out the ip2k port again.. the last time I looked, I was  
> blinded by the assumption that if the usual stack macros were  
> defined in a straightforward fashion, that the target actually  
> supported (or implemented) a stack... "It ain't necessarily so".
>
> > you might be able to keep the SP as a virtual register and make sure
> > that code generation never tries to actually use it