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Re: Design a microcontroller for gcc
On Wed, 15 Feb 2006, DJ Delorie wrote:
> > BTW, carry-out from shifts is very rarely used in compiled code.)
> Unless you've expanded SI shifts into a pair of HI shifts.
>
> > Besides what DJ said about performance (both pros and cons
> > there), the problem is as I said with port complexity, because
> > of the way you have to handle condition codes in gcc.
>
> Unless you tell gcc that the condition codes are hard register?
No "unless" here. You either have a clobber or a set in a
parallel with the main feature, and you lose out on all the
single_set-directed optimizations if you put in a "set" early.
> That's what m32c does; it has separate cmp/jmp and most opcodes set
> flags, so I just set an attribute that says which flags are set by
> each insn. Then, I can add a reorg pass to delete the cmps if the
> previous insn that set the flags happened to set them right.
A machine dependent reorg pass isn't something I'd recommend
given that there are other possibilities. FWIW, I use
peephole2s and condition code modes in CRIS w.i.p. Works ok,
except for all the things that doesn't like insns with parallels
that I have to weed out to get performance on par with the cc0
representation.
brgds, H-P