Re: Design a microcontroller for gcc

[Hans-Peter Nilsson <hp at bitrange dot com>]

On Thu, 16 Feb 2006, Sylvain Munaut wrote:
> What I was thinking for the moment was to have :
>  - sign is always the msb of the last ALU output
>  - add/sub to modify all flags
>  - move/xor/and/not/or only affect zero (and sign)
>  - shift operations always affect carry and zero
>  - Have some specific instructions like compare and test, but theses
>    would only operate on registers (and not on immediate)

No, really.  Just use compare insns.  (And perhaps some way for
carry propagation for multi-word add/sub, if that mechanism
interferes.  BTW, carry-out from shifts is very rarely used in
compiled code.)

> What's so bad about have the flag as side-effects ?

Besides what DJ said about performance (both pros and cons
there), the problem is as I said with port complexity, because
of the way you have to handle condition codes in gcc.
(_Should_ now, _have_to_ in the future -- or actually now, as
you say you need scheduling.)  Flag setting really should be
explicit, so with your way, you have to show that add and sub
etc. also set condition codes.  And that's where you notice the
complexity in the port, because (partly because of gcc
pecularities) unless you want to lose performancewise, you need
to show that most of the time, the flag register result is just
clobbered by those operations and not used.  Anyway, at least
keep a way to add reg+reg and reg+integer, load and store of
memory and load of integer and address without condition code
effects and your port has a chance to avoid the related bloat.

Sorry, I won't spend the time to spell out the details.
Whatever: if you're determined on your way to do it and won't
take advice you asked for, by all means feel free.  You _have_
been warned, though.

brgds, H-P