improved ia64 atomic ops

["Jan Beulich" <JBeulich at novell dot com>]

Richard,

in the context of internal discussions regarding target/24757 I have
been made aware of a change to the sync operations on ia64, and I have
problems understanding

>    This differs from the generic code in that we know about the
zero-extending
>    properties of cmpxchg, and the zero-extending requirements of
ar.ccv.  We
>    also know that ld.acq+cmpxchg.rel equals a full barrier.

Namely, while ld.acq is guaranteed to execute/become visible before the
cmpxchg.rel, it is not guaranteed to execute after any preceding ld, st,
or st.rel; similarly the cmpxchg.rel, while definitely getting executed
after the ld.acq, there's no guarantee that there'll be no subsequent
operations (ld, ld.acq, st) executed prior to it. Thus the previous
behavior (where a fence was the first thing, and because of that plus
the use of cmpxchg.acq there was full separation backward and forward)
isn't being retained.

I think that only the inverse (initial .rel and final .acq) can be
viewed as a replacement for a full fence, with the caveat that these two
then aren't ordered wrt one another. But since there's no ld.rel, an
initial fence is unavoidable.

What am I missing?

Jan