Question of `internal consistency failure' in the backend pass 32 (sched2)

["Ling-hua Tseng" <uranus at it dot muds dot net>]

My GCC version is gcc version 4.0.1 20050630 (prerelease).

I got an error `internal consistency failure' in the backend pass 32.
This error was generated by flow.c:verify_local_live_at_start().
The RTL dump, <file>.c.32.sched2, printed:
--------------------------------[begin]-------------------------------
live_at_start mismatch in bb 0, aborting
New:

first = 0x84053cc current = 0x84053cc indx = 0
       0x84053cc next = (nil) prev = (nil) indx = 0
               bits = { 2 11 14 15 }
Old:
;; basic block 0, loop depth 0, count 0
;; prev block -1, next block -2
;; pred:       ENTRY [100.0%]  (fallthru)
;; succ:       EXIT [100.0%] 
;; Registers live at start:  2 [r2] 3 [r3] 11 [r11] 14 [r14] 15 [r15]
---------------------------------[end]--------------------------------

The r2 and r3 are represented a V8QI register (a double-word data).
Now I described the major processes about r2 and r3 in the backend.

1. In the <file>.c.00.expand, it was expanded to:
(insn 12 11 13 1 (set (reg:V8QI 107)
       (const_vector:V8QI [
               (const_int -86 [0xffffffaa])
               (const_int -69 [0xffffffbb])
               (const_int -52 [0xffffffcc])
               (const_int -35 [0xffffffdd])
               (const_int -18 [0xffffffee])
               (const_int -1 [0xffffffff])
               (const_int 18 [0x12])
               (const_int 52 [0x34])
           ])) -1 (nil)
   (nil))

2. In the <file>.c.23.sched, it was split to 4 RTXs:
(insn 33 10 34 0 (set (vec_select:HI (subreg:V4QI (reg:V8QI 107) 0)
           (parallel [
                   (const_int 0 [0x0])
                   (const_int 1 [0x1])
               ]))
       (const_int 48042 [0xbbaa])) 1 {*movv4qi_lowpart} (nil)
   (nil))

(insn 34 33 35 0 (set (vec_select:HI (subreg:V4QI (reg:V8QI 107) 0)
           (parallel [
                   (const_int 2 [0x2])
                   (const_int 3 [0x3])
               ]))
       (const_int 56780 [0xddcc])) 2 {*movv4qi_highpart} (nil)
   (nil))

(insn 35 34 36 0 (set (vec_select:HI (subreg:V4QI (reg:V8QI 107) 4)
           (parallel [
                   (const_int 0 [0x0])
                   (const_int 1 [0x1])
               ]))
       (const_int 65518 [0xffee])) 1 {*movv4qi_lowpart} (nil)
   (nil))

(insn 36 35 11 0 (set (vec_select:HI (subreg:V4QI (reg:V8QI 107) 4)
           (parallel [
                   (const_int 2 [0x2])
                   (const_int 3 [0x3])
               ]))
       (const_int 13330 [0x3412])) 2 {*movv4qi_highpart} (nil)
   (nil))

3. In the <file>.c.23.greg, the pass did `reload_in_reg: (reg:V8QI 2 r2 [107])':
(insn 33 11 34 0 (set (vec_select:HI (reg:V4QI 2 r2 [107])
           (parallel [
                   (const_int 0 [0x0])
                   (const_int 1 [0x1])
               ]))
       (const_int 48042 [0xbbaa])) 1 {*movv4qi_lowpart} (nil)
   (nil))

(insn 34 33 35 0 (set (vec_select:HI (reg:V4QI 2 r2 [107])
           (parallel [
                   (const_int 2 [0x2])
                   (const_int 3 [0x3])
               ]))
       (const_int 56780 [0xddcc])) 2 {*movv4qi_highpart} (nil)
   (nil))

(insn 35 34 36 0 (set (vec_select:HI (reg:V4QI 3 r3 [+4 ])
           (parallel [
                   (const_int 0 [0x0])
                   (const_int 1 [0x1])
               ]))
       (const_int 65518 [0xffee])) 1 {*movv4qi_lowpart} (nil)
   (nil))

(insn 36 35 13 0 (set (vec_select:HI (reg:V4QI 3 r3 [+4 ])
           (parallel [
                   (const_int 2 [0x2])
                   (const_int 3 [0x3])
               ]))
       (const_int 13330 [0x3412])) 2 {*movv4qi_highpart} (nil)
   (nil))

Because it's a double-word pseudo register,
the register allocator allocated 2 registers (r2 and r3).
The 4 RTXs will not be changed in the future passes.
Finally, the error was occured in the pass 32.

The information of <file>.c.32.sched2 seems to tell me that
there are something wrong with register live bitmap in the CFG.
The bitmap is { 2 11 14 15 },
and I believe that it should be { 2 "3" 11 14 15 }.

Thus, I guess that I missed some configurations in the target hooks or target machine macros.
Would anyone like to tell me what hooks/macros could afffect the live bitmaps in the CFG?

Thanks a lot.