;; Function __ieee754_sqrt ;; 17 regs to allocate: 83 79 168 77 74 75 70 (2) 71 (2) 131 84 80 82 76 81 78 72 (2) 153 (2) ;; 70 conflicts: 70 71 77 79 97 153 0 17 18 20 30 ;; 71 conflicts: 70 71 77 79 85 86 91 97 101 104 153 0 1 4 5 6 16 17 18 19 20 30 ;; 72 conflicts: 72 78 81 82 143 153 0 16 17 18 19 20 30 ;; 73 conflicts: 73 74 76 77 78 79 80 81 82 153 0 20 30 ;; 74 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30 ;; 75 conflicts: 74 75 76 77 78 79 80 81 82 83 131 133 134 153 164 168 170 0 1 20 30 ;; 76 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30 ;; 77 conflicts: 70 71 73 74 75 76 77 78 79 80 81 82 83 84 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 153 155 164 168 170 0 1 17 18 20 30 ;; 78 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 143 148 149 153 164 168 170 176 177 0 1 16 17 18 19 20 30 ;; 79 conflicts: 70 71 73 74 75 76 77 78 79 80 81 82 83 84 85 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 153 155 164 168 170 0 1 17 18 20 30 ;; 80 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30 ;; 81 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 143 148 149 153 164 168 170 176 177 0 1 16 17 18 19 20 30 ;; 82 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 84 113 114 116 118 120 122 123 125 126 128 129 131 133 134 136 137 143 148 149 153 155 164 168 170 176 177 0 1 16 17 18 19 20 30 ;; 83 conflicts: 74 75 76 77 78 79 80 81 82 83 131 133 134 153 164 168 170 0 1 20 30 ;; 84 conflicts: 77 79 82 84 114 115 116 118 153 155 0 20 30 ;; 85 conflicts: 71 79 85 153 0 1 17 18 20 30 ;; 86 conflicts: 71 77 79 86 153 0 17 18 20 30 ;; 91 conflicts: 71 91 18 19 20 30 ;; 97 conflicts: 70 71 77 79 97 153 0 17 18 20 30 ;; 101 conflicts: 71 101 104 0 4 5 6 16 17 18 19 20 30 ;; 104 conflicts: 71 101 104 108 0 1 4 5 6 16 17 18 19 20 30 ;; 108 conflicts: 104 108 0 1 4 5 17 18 19 20 30 ;; 113 conflicts: 77 79 82 113 153 0 20 30 ;; 114 conflicts: 77 79 82 84 114 153 0 20 30 ;; 115 conflicts: 77 79 84 115 153 0 20 30 ;; 116 conflicts: 77 79 82 84 116 153 0 20 30 ;; 118 conflicts: 77 79 82 84 118 153 0 20 30 ;; 120 conflicts: 77 79 82 120 153 0 20 30 ;; 122 conflicts: 77 79 82 122 153 0 20 30 ;; 123 conflicts: 77 79 82 123 153 0 20 30 ;; 125 conflicts: 77 79 82 125 153 0 20 30 ;; 126 conflicts: 77 79 82 126 153 0 20 30 ;; 128 conflicts: 74 76 77 78 79 80 81 82 128 153 0 20 30 ;; 129 conflicts: 74 76 77 78 79 80 81 82 129 153 0 20 30 ;; 131 conflicts: 74 75 76 77 78 79 80 81 82 83 131 153 168 20 30 ;; 133 conflicts: 74 75 76 77 78 79 80 81 82 83 133 153 0 20 30 ;; 134 conflicts: 74 75 76 77 78 79 80 81 82 83 134 153 170 0 1 20 30 ;; 136 conflicts: 74 76 77 78 79 80 81 82 136 153 0 20 30 ;; 137 conflicts: 74 76 77 78 79 80 81 82 137 153 0 20 30 ;; 143 conflicts: 72 78 81 82 143 153 18 20 30 ;; 148 conflicts: 78 81 82 148 153 18 20 30 ;; 149 conflicts: 78 81 82 149 153 0 20 30 ;; 153 conflicts: 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 143 148 149 153 155 164 168 170 176 177 0 1 16 17 18 19 20 30 ;; 155 conflicts: 77 79 82 84 153 155 0 20 30 ;; 164 conflicts: 74 75 76 77 78 79 80 81 82 83 153 164 168 0 20 30 ;; 168 conflicts: 74 75 76 77 78 79 80 81 82 83 131 153 164 168 0 20 30 ;; 170 conflicts: 74 75 76 77 78 79 80 81 82 83 134 153 170 0 1 20 30 ;; 176 conflicts: 78 81 82 153 176 177 0 1 20 30 ;; 177 conflicts: 78 81 82 153 176 177 0 1 20 30 Spilling for insn 581. Using reg 0 for reload 0 Using reg 2 for reload 1 Spilling for insn 26. Spilling for insn 61. Spilling for insn 111. Spilling for insn 131. Spilling for insn 528. Spilling for insn 147. Spilling for insn 168. Spilling for insn 172. Spilling for insn 173. Using reg 2 for reload 0 Spilling for insn 184. Spilling for insn 191. Spilling for insn 201. Spilling for insn 225. Spilling for insn 232. Spilling for insn 240. Spilling for insn 269. Spilling for insn 562. Spilling for insn 563. Spilling for insn 294. Spilling for insn 296. Spilling for insn 299. Spilling for insn 568. Spilling for insn 320. Spilling for insn 574. Spilling for insn 575. Spilling for insn 403. Spilling for insn 410. Spilling for insn 413. Spilling for insn 429. Using reg 0 for reload 0 Spilling for insn 431. Using reg 0 for reload 0 Using reg 2 for reload 1 Spilling for insn 433. Using reg 0 for reload 0 Using reg 0 for reload 1 Reloads for insn # 581 Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p reload_reg_rtx: (reg:DI 0 r0) Reload 1: reload_out (DI) = (reg/v:DI 153) GPR_REGS, RELOAD_FOR_OUTPUT (opnum = 0) reload_out_reg: (reg/v:DI 153) reload_reg_rtx: (reg:DI 2 r2) secondary_out_reload = 0 Reloads for insn # 26 Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79]) reload_out (SI) = (reg:SI 0 r0 [86]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 3 r3 [79]) reload_out_reg: (reg:SI 0 r0 [86]) reload_reg_rtx: (reg:SI 0 r0 [86]) Reloads for insn # 61 Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79]) reload_out (SI) = (reg:SI 0 r0 [97]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 3 r3 [79]) reload_out_reg: (reg:SI 0 r0 [97]) reload_reg_rtx: (reg:SI 0 r0 [97]) Reloads for insn # 111 Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79]) reload_out (SI) = (reg/v:SI 4 r4 [82]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 3 r3 [79]) reload_out_reg: (reg/v:SI 4 r4 [82]) reload_reg_rtx: (reg/v:SI 4 r4 [82]) Reloads for insn # 131 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [113]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [113]) reload_reg_rtx: (reg:SI 0 r0 [113]) Reloads for insn # 528 Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79]) reload_out (SI) = (reg:SI 0 r0 [155]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 3 r3 [79]) reload_out_reg: (reg:SI 0 r0 [155]) reload_reg_rtx: (reg:SI 0 r0 [155]) Reloads for insn # 147 Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79]) reload_out (SI) = (reg/s:SI 0 r0 [114]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 3 r3 [79]) reload_out_reg: (reg/s:SI 0 r0 [114]) reload_reg_rtx: (reg/s:SI 0 r0 [114]) Reloads for insn # 168 Reload 0: reload_in (SI) = (reg/v:SI 4 r4 [82]) reload_out (SI) = (reg:SI 0 r0 [115]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 4 r4 [82]) reload_out_reg: (reg:SI 0 r0 [115]) reload_reg_rtx: (reg:SI 0 r0 [115]) Reloads for insn # 172 Reload 0: reload_in (SI) = (reg/v:SI 1 r1 [84]) reload_out (SI) = (reg:SI 0 r0 [116]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 1 r1 [84]) reload_out_reg: (reg:SI 0 r0 [116]) reload_reg_rtx: (reg:SI 0 r0 [116]) Reloads for insn # 173 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [118]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [118]) reload_reg_rtx: (reg:SI 2 r2) Reloads for insn # 184 Reload 0: reload_in (SI) = (reg/v:SI 4 r4 [82]) reload_out (SI) = (reg:SI 0 r0 [120]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 4 r4 [82]) reload_out_reg: (reg:SI 0 r0 [120]) reload_reg_rtx: (reg:SI 0 r0 [120]) Reloads for insn # 191 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [122]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [122]) reload_reg_rtx: (reg:SI 0 r0 [122]) Reloads for insn # 201 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [125]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [125]) reload_reg_rtx: (reg:SI 0 r0 [125]) Reloads for insn # 225 Reload 0: reload_in (SI) = (reg/v:SI 15 r15 [80]) reload_out (SI) = (reg/v:SI 2 r2 [83]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 15 r15 [80]) reload_out_reg: (reg/v:SI 2 r2 [83]) reload_reg_rtx: (reg/v:SI 2 r2 [83]) Reloads for insn # 232 Reload 0: reload_in (SI) = (reg/v:SI 2 r2 [83]) reload_out (SI) = (reg/v:SI 15 r15 [80]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 2 r2 [83]) reload_out_reg: (reg/v:SI 15 r15 [80]) reload_reg_rtx: (reg/v:SI 15 r15 [80]) Reloads for insn # 240 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [128]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [128]) reload_reg_rtx: (reg:SI 0 r0 [128]) Reloads for insn # 269 Reload 0: reload_in (SI) = (reg/v:SI 17 r17 [76]) reload_out (SI) = (reg/v:SI 14 r14 [75]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 17 r17 [76]) reload_out_reg: (reg/v:SI 14 r14 [75]) reload_reg_rtx: (reg/v:SI 14 r14 [75]) Reloads for insn # 562 Reload 0: reload_in (SI) = (reg/v:SI 2 r2 [83]) reload_out (SI) = (reg:SI 0 r0 [164]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 2 r2 [83]) reload_out_reg: (reg:SI 0 r0 [164]) reload_reg_rtx: (reg:SI 0 r0 [164]) Reloads for insn # 563 Reload 0: reload_in (SI) = (reg:SI 0 r0 [164]) reload_out (SI) = (reg:SI 1 r1 [168]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg:SI 0 r0 [164]) reload_out_reg: (reg:SI 1 r1 [168]) reload_reg_rtx: (reg:SI 1 r1 [168]) Reloads for insn # 294 Reload 0: reload_in (SI) = (reg/v:SI 14 r14 [75]) reload_out (SI) = (reg/v:SI 17 r17 [76]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 14 r14 [75]) reload_out_reg: (reg/v:SI 17 r17 [76]) reload_reg_rtx: (reg/v:SI 17 r17 [76]) Reloads for insn # 296 Reload 0: reload_in (SI) = (reg/v:SI 14 r14 [75]) reload_out (SI) = (reg:SI 0 r0 [133]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 14 r14 [75]) reload_out_reg: (reg:SI 0 r0 [133]) reload_reg_rtx: (reg:SI 0 r0 [133]) Reloads for insn # 299 Reload 0: reload_in (SI) = (reg/v:SI 17 r17 [76]) reload_out (SI) = (reg:SI 1 r1 [134]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 17 r17 [76]) reload_out_reg: (reg:SI 1 r1 [134]) reload_reg_rtx: (reg:SI 1 r1 [134]) Reloads for insn # 568 Reload 0: reload_in (SI) = (reg:SI 1 r1 [134]) reload_out (SI) = (reg:SI 0 r0 [170]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg:SI 1 r1 [134]) reload_out_reg: (reg:SI 0 r0 [170]) reload_reg_rtx: (reg:SI 0 r0 [170]) Reloads for insn # 320 Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77]) reload_out (SI) = (reg:SI 0 r0 [136]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 12 r12 [77]) reload_out_reg: (reg:SI 0 r0 [136]) reload_reg_rtx: (reg:SI 0 r0 [136]) Reloads for insn # 574 Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78]) reload_out (SI) = (reg:SI 1 r1 [176]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 8 r8 [78]) reload_out_reg: (reg:SI 1 r1 [176]) reload_reg_rtx: (reg:SI 1 r1 [176]) Reloads for insn # 575 Reload 0: reload_in (SI) = (reg:SI 1 r1 [176]) reload_out (SI) = (reg:SI 0 r0 [177]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg:SI 1 r1 [176]) reload_out_reg: (reg:SI 0 r0 [177]) reload_reg_rtx: (reg:SI 0 r0 [177]) Reloads for insn # 403 Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78]) reload_out (SI) = (reg:SI 0 r0 [149]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 8 r8 [78]) reload_out_reg: (reg:SI 0 r0 [149]) reload_reg_rtx: (reg:SI 0 r0 [149]) Reloads for insn # 410 Reload 0: reload_in (SI) = (reg/v:SI 6 r6 [81]) reload_out (SI) = (reg/v:SI 3 r3 [79]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 6 r6 [81]) reload_out_reg: (reg/v:SI 3 r3 [79]) reload_reg_rtx: (reg/v:SI 3 r3 [79]) Reloads for insn # 413 Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78]) reload_out (SI) = (reg/v:SI 12 r12 [77]) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 8 r8 [78]) reload_out_reg: (reg/v:SI 12 r12 [77]) reload_reg_rtx: (reg/v:SI 12 r12 [77]) Reloads for insn # 429 Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p reload_reg_rtx: (reg:SI 0 r0) Reload 1: reload_in (SI) = (reg/v:SI 4 r4 [82]) reload_out (SI) = (subreg:SI (reg/v:DI 153) 4) GPR_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (reg/v:SI 4 r4 [82]) reload_out_reg: (subreg:SI (reg/v:DI 153) 4) reload_reg_rtx: (reg/v:SI 4 r4 [82]) secondary_out_reload = 0 Reloads for insn # 431 Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p reload_reg_rtx: (reg:DI 2 r2) Reload 1: reload_out (DI) = (reg/v:DI 153) GPR_REGS, RELOAD_FOR_OUTPUT (opnum = 0) reload_out_reg: (reg/v:DI 153) reload_reg_rtx: (reg:DI 0 r0) secondary_out_reload = 0 Reloads for insn # 433 Reload 0: ADDR32_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1), can't combine, secondary_reload_p reload_reg_rtx: (reg:DI 2 r2) Reload 1: reload_in (DI) = (reg/v:DI 153) GPR_REGS, RELOAD_FOR_INPUT (opnum = 1) reload_in_reg: (reg/v:DI 153) reload_reg_rtx: (reg:DI 0 r0) secondary_in_reload = 0 ;; Register dispositions: 70 in 14 71 in 8 72 in 10 73 in 0 74 in 13 75 in 14 76 in 17 77 in 12 78 in 8 79 in 3 80 in 15 81 in 6 82 in 4 83 in 2 84 in 1 85 in 0 86 in 0 91 in 18 97 in 0 101 in 6 104 in 4 108 in 0 113 in 0 114 in 0 115 in 0 116 in 0 118 in 0 120 in 0 122 in 0 123 in 0 125 in 0 126 in 0 128 in 0 129 in 0 131 in 0 133 in 0 134 in 1 136 in 0 137 in 0 143 in 18 148 in 18 149 in 0 155 in 0 164 in 0 168 in 1 170 in 0 176 in 1 177 in 0 ;; Hard regs used: 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 64 (note 1 0 450 ("sqrt.c") 15) ;; Start of basic block 0, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] (note 450 1 581 0 [bb 0] NOTE_INSN_BASIC_BLOCK) (insn 581 450 587 0 0x0 (set (reg:DI 2 r2) (const_int 0 [0x0])) 7 {*movdi} (nil) (nil)) (insn 587 581 588 0 0x0 (set (reg:DI 0 r0) (reg:DI 2 r2)) 7 {*movdi} (nil) (nil)) (insn 588 587 3 0 0x0 (set (mem:DI (plus:SI (reg/f:SI 21 r21) (const_int -8 [0xfffffff8])) [3 iw_u S8 A32]) (reg:DI 0 r0)) 7 {*movdi} (nil) (nil)) (insn 3 588 4 0 0x0 (set (reg/v:DF 8 r8 [71]) (reg:DF 17 r17)) 10 {*movdf} (nil) (nil)) (note 4 3 8 0 NOTE_INSN_FUNCTION_BEG) (note 8 4 9 0 ("sqrt.c") 16) (note 9 8 11 0 ("sqrt.c") 17) (note 11 9 12 0 ("sqrt.c") 18) (note 12 11 16 0 ("sqrt.c") 19) (note 16 12 17 0 ("sqrt.c") 23) (note 17 16 18 0 ("sqrt.c") 24) (insn 18 17 19 0 0x1002f390 (set (reg:DF 0 r0 [85]) (reg/v:DF 8 r8 [71])) 10 {*movdf} (insn_list 3 (nil)) (nil)) (note 19 18 20 0 ("sqrt.c") 25) (insn 20 19 21 0 0x1002f390 (set (reg/v:SI 3 r3 [79]) (reg:SI 1 r1)) 6 {*movsi} (insn_list 18 (nil)) (nil)) (note 21 20 22 0 ("sqrt.c") 26) (insn 22 21 25 0 0x1002f390 (set (reg/v:SI 12 r12 [77]) (reg:SI 0 r0 [85])) 6 {*movsi} (nil) (nil)) (note 25 22 589 0 ("sqrt.c") 31) (insn 589 25 26 0 0x0 (set (reg:SI 0 r0 [86]) (reg/v:SI 3 r3 [79])) 6 {*movsi} (nil) (nil)) (insn 26 589 27 0 0x1002f450 (set (reg:SI 0 r0 [86]) (and:SI (reg:SI 0 r0 [86]) (const_int 2146435072 [0x7ff00000]))) 25 {andsi3} (insn_list 20 (nil)) (nil)) (insn:QI 27 26 28 0 0x1002f450 (set (cc0) (compare:SI (reg:SI 0 r0 [86]) (const_int 2146435072 [0x7ff00000]))) 29 {cmpsi_internal} (insn_list 26 (nil)) (nil)) (jump_insn 28 27 31 0 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 53) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 7100 [0x1bbc]) (nil))) ;; End of basic block 0, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153 (note 31 28 452 ("sqrt.c") 33) ;; Start of basic block 1, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 (note 452 31 34 1 [bb 1] NOTE_INSN_BASIC_BLOCK) (note 34 452 38 1 NOTE_INSN_DELETED) (insn 38 34 39 1 0x1002f450 (set (reg:SI 19 r19) (reg:SI 8 r8 [71])) 6 {*movsi} (nil) (nil)) (insn 39 38 40 1 0x1002f450 (set (reg:SI 0 r0) (reg:SI 9 r9)) 6 {*movsi} (nil) (nil)) (call_insn/u 40 39 41 1 0x1002f450 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (symbol_ref:SI ("__muldf3")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 39 (insn_list 38 (nil))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 41 40 42 1 0x1002f450 (set (reg:DF 18 r18 [91]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 40 (nil)) (expr_list:REG_EQUAL (mult:DF (reg:DF 17 r17) (reg:DF 17 r17)) (nil))) (note 42 41 43 1 NOTE_INSN_DELETED) (insn 43 42 46 1 0x1002f450 (set (reg:DF 17 r17) (reg:DF 18 r18 [91])) 10 {*movdf} (insn_list 41 (nil)) (nil)) (insn 46 43 47 1 0x1002f450 (set (reg:SI 19 r19) (reg:SI 8 r8 [71])) 6 {*movsi} (nil) (nil)) (insn 47 46 48 1 0x1002f450 (set (reg:SI 0 r0) (reg:SI 9 r9)) 6 {*movsi} (nil) (nil)) (call_insn/u 48 47 49 1 0x1002f450 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (symbol_ref:SI ("__adddf3")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 47 (insn_list 46 (insn_list 43 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 49 48 51 1 0x1002f450 (set (reg:DF 14 r14 [70]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 48 (nil)) (expr_list:REG_EQUAL (plus:DF (reg:DF 18 r18 [91]) (reg/v:DF 8 r8 [71])) (nil))) (jump_insn 51 49 52 1 0x1002f450 (set (pc) (label_ref 445)) 35 {jump} (nil) (nil)) ;; End of basic block 1, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 (barrier 52 51 53) ;; Start of basic block 2, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153 (code_label 53 52 453 2 3 "" [1 uses]) (note 453 53 54 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 54 453 55 2 ("sqrt.c") 37) (insn:QI 55 54 56 2 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 3 r3 [79]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 56 55 59 2 0x1002f450 (set (pc) (if_then_else (gt (cc0) (const_int 0 [0x0])) (label_ref 109) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 7900 [0x1edc]) (nil))) ;; End of basic block 2, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153 (note 59 56 454 ("sqrt.c") 39) ;; Start of basic block 3, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153 (note 454 59 590 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 590 454 61 3 0x0 (set (reg:SI 0 r0 [97]) (reg/v:SI 3 r3 [79])) 6 {*movsi} (nil) (nil)) (insn 61 590 62 3 0x1002f450 (set (reg:SI 0 r0 [97]) (and:SI (reg:SI 0 r0 [97]) (const_int 2147483647 [0x7fffffff]))) 25 {andsi3} (nil) (nil)) (insn 62 61 68 3 0x1002f450 (set (reg:SI 0 r0 [97]) (ior:SI (reg:SI 0 r0 [97]) (reg/v:SI 12 r12 [77]))) 26 {iorsi3} (insn_list 61 (nil)) (nil)) (insn 68 62 63 3 0x1002f450 (set (reg:DF 14 r14 [70]) (reg/v:DF 8 r8 [71])) 10 {*movdf} (nil) (nil)) (insn:QI 63 68 64 3 0x1002f450 (set (cc0) (compare:SI (reg:SI 0 r0 [97]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 62 (nil)) (nil)) (jump_insn 64 63 65 3 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 445) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 3, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 71 77 79 153 (note 65 64 457 ("sqrt.c") 40) ;; Start of basic block 5, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153 (note 457 65 74 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (note 74 457 75 5 ("sqrt.c") 41) (insn:QI 75 74 76 5 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 3 r3 [79]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 76 75 77 5 0x1002f450 (set (pc) (if_then_else (ge (cc0) (const_int 0 [0x0])) (label_ref 109) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 7900 [0x1edc]) (nil))) ;; End of basic block 5, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153 (note 77 76 458 ("sqrt.c") 42) ;; Start of basic block 6, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 (note 458 77 80 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (insn 80 458 84 6 0x1002f450 (set (reg/f:SI 6 r6 [101]) (symbol_ref:SI ("__subdf3"))) 6 {*movsi} (nil) (expr_list:REG_EQUIV (symbol_ref:SI ("__subdf3")) (nil))) (insn 84 80 85 6 0x1002f450 (set (reg:SI 19 r19) (reg:SI 8 r8 [71])) 6 {*movsi} (nil) (nil)) (insn 85 84 86 6 0x1002f450 (set (reg:SI 0 r0) (reg:SI 9 r9)) 6 {*movsi} (nil) (nil)) (call_insn/u 86 85 87 6 0x1002f450 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (reg/f:SI 6 r6 [101]) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 80 (insn_list 84 (insn_list 85 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 87 86 89 6 0x1002f450 (set (reg:DF 4 r4 [104]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 86 (nil)) (expr_list:REG_EQUAL (minus:DF (reg:DF 17 r17) (reg:DF 17 r17)) (nil))) (insn 89 87 92 6 0x1002f450 (set (reg:DF 17 r17) (reg/v:DF 8 r8 [71])) 10 {*movdf} (nil) (nil)) (insn 92 89 93 6 0x1002f450 (set (reg:SI 19 r19) (reg:SI 17 r17)) 6 {*movsi} (nil) (nil)) (insn 93 92 94 6 0x1002f450 (set (reg:SI 0 r0) (reg:SI 18 r18)) 6 {*movsi} (nil) (nil)) (call_insn/u 94 93 95 6 0x1002f450 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (reg/f:SI 6 r6 [101]) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 89 (insn_list 92 (insn_list 93 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 95 94 96 6 0x1002f450 (set (reg:DF 0 r0 [108]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 94 (nil)) (expr_list:REG_EQUAL (minus:DF (reg/v:DF 8 r8 [71]) (reg/v:DF 8 r8 [71])) (nil))) (note 96 95 97 6 NOTE_INSN_DELETED) (insn 97 96 100 6 0x1002f450 (set (reg:DF 17 r17) (reg:DF 4 r4 [104])) 10 {*movdf} (insn_list 87 (nil)) (nil)) (insn 100 97 101 6 0x1002f450 (set (reg:SI 19 r19) (reg:SI 0 r0 [108])) 6 {*movsi} (insn_list 95 (nil)) (nil)) (insn 101 100 102 6 0x1002f450 (set (reg:SI 0 r0) (reg:SI 1 r1)) 6 {*movsi} (nil) (nil)) (call_insn/u 102 101 103 6 0x1002f450 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (symbol_ref:SI ("__divdf3")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 101 (insn_list 100 (insn_list 97 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 103 102 105 6 0x1002f450 (set (reg:DF 14 r14 [70]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 102 (nil)) (expr_list:REG_EQUAL (div:DF (reg:DF 4 r4 [104]) (reg:DF 0 r0 [108])) (nil))) (jump_insn 105 103 106 6 0x1002f450 (set (pc) (label_ref 445)) 35 {jump} (nil) (nil)) ;; End of basic block 6, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 (barrier 106 105 109) ;; Start of basic block 7, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 153 (code_label 109 106 461 7 4 "" [2 uses]) (note 461 109 110 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (note 110 461 591 7 ("sqrt.c") 45) (insn 591 110 111 7 0x0 (set (reg/v:SI 4 r4 [82]) (reg/v:SI 3 r3 [79])) 6 {*movsi} (nil) (nil)) (insn 111 591 112 7 0x1002f450 (set (reg/v:SI 4 r4 [82]) (ashiftrt:SI (reg/v:SI 4 r4 [82]) (const_int 20 [0x14]))) 23 {ashrsi3} (nil) (nil)) (note 112 111 113 7 ("sqrt.c") 46) (insn:QI 113 112 114 7 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 4 r4 [82]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 111 (nil)) (nil)) (jump_insn 114 113 117 7 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 177) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 7, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 (note 117 114 550 ("sqrt.c") 48) ;; Start of basic block 8, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (note 550 117 521 8 [bb 8] NOTE_INSN_BASIC_BLOCK) (insn:QI 521 550 522 8 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 3 r3 [79]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 522 521 118 8 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 523) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 3600 [0xe10]) (nil))) ;; End of basic block 8, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 (note 118 522 136 NOTE_INSN_LOOP_BEG) ;; Start of basic block 9, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (code_label 136 118 463 9 12 "" [1 uses]) (note 463 136 128 9 [bb 9] NOTE_INSN_BASIC_BLOCK) (note 128 463 129 9 ("sqrt.c") 50) (insn 129 128 130 9 0x1002f450 (set (reg/v:SI 4 r4 [82]) (plus:SI (reg/v:SI 4 r4 [82]) (const_int -21 [0xffffffeb]))) 12 {addsi3} (nil) (nil)) (note 130 129 592 9 ("sqrt.c") 51) (insn 592 130 131 9 0x0 (set (reg:SI 0 r0 [113]) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 131 592 132 9 0x1002f450 (set (reg:SI 0 r0 [113]) (lshiftrt:SI (reg:SI 0 r0 [113]) (const_int 11 [0xb]))) 24 {lshrsi3} (nil) (nil)) (insn 132 131 133 9 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ior:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [113]))) 26 {iorsi3} (insn_list 131 (nil)) (nil)) (note 133 132 134 9 ("sqrt.c") 52) (insn 134 133 135 9 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (const_int 21 [0x15]))) 22 {ashlsi3} (nil) (nil)) (note 135 134 527 9 NOTE_INSN_LOOP_CONT) (note 527 135 120 9 NOTE_INSN_LOOP_VTOP) (insn:QI 120 527 121 9 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 3 r3 [79]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 132 (nil)) (nil)) (jump_insn 121 120 141 9 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 136) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 8900 [0x22c4]) (nil))) ;; End of basic block 9, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 (note 141 121 523 NOTE_INSN_LOOP_END) ;; Start of basic block 10, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (code_label 523 141 467 10 46 "" [1 uses]) (note 467 523 143 10 [bb 10] NOTE_INSN_BASIC_BLOCK) (note 143 467 144 10 ("sqrt.c") 54) (insn 144 143 593 10 0x1002f450 (set (reg/v:SI 1 r1 [84]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (insn 593 144 528 10 0x0 (set (reg:SI 0 r0 [155]) (reg/v:SI 3 r3 [79])) 6 {*movsi} (nil) (nil)) (insn 528 593 529 10 0x1002f450 (set (reg:SI 0 r0 [155]) (and:SI (reg:SI 0 r0 [155]) (const_int 1048576 [0x100000]))) 25 {andsi3} (nil) (nil)) (insn:QI 529 528 530 10 0x1002f450 (set (cc0) (compare:SI (reg:SI 0 r0 [155]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 528 (nil)) (nil)) (jump_insn 530 529 145 10 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 531) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 3600 [0xe10]) (nil))) ;; End of basic block 10, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153 (note 145 530 160 NOTE_INSN_LOOP_BEG) ;; Start of basic block 11, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 84 153 (code_label 160 145 468 11 17 "" [1 uses]) (note 468 160 154 11 [bb 11] NOTE_INSN_BASIC_BLOCK) (note 154 468 155 11 ("sqrt.c") 55) (insn 155 154 156 11 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ashift:SI (reg/v:SI 3 r3 [79]) (const_int 1 [0x1]))) 22 {ashlsi3} (nil) (nil)) (note 156 155 157 11 ("sqrt.c") 54) (note 157 156 159 11 NOTE_INSN_LOOP_CONT) (insn 159 157 535 11 0x1002f450 (set (reg/v:SI 1 r1 [84]) (plus:SI (reg/v:SI 1 r1 [84]) (const_int 1 [0x1]))) 12 {addsi3} (nil) (nil)) (note 535 159 594 11 NOTE_INSN_LOOP_VTOP) (insn 594 535 147 11 0x0 (set (reg/s:SI 0 r0 [114]) (reg/v:SI 3 r3 [79])) 6 {*movsi} (nil) (nil)) (insn 147 594 148 11 0x1002f450 (set (reg/s:SI 0 r0 [114]) (and:SI (reg/s:SI 0 r0 [114]) (const_int 1048576 [0x100000]))) 25 {andsi3} (insn_list 155 (nil)) (nil)) (insn:QI 148 147 149 11 0x1002f450 (set (cc0) (compare:SI (reg/s:SI 0 r0 [114]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 147 (nil)) (nil)) (jump_insn 149 148 165 11 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 160) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 8900 [0x22c4]) (nil))) ;; End of basic block 11, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153 (note 165 149 531 NOTE_INSN_LOOP_END) ;; Start of basic block 12, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 84 153 (code_label 531 165 473 12 48 "" [1 uses]) (note 473 531 167 12 [bb 12] NOTE_INSN_BASIC_BLOCK) (note 167 473 595 12 ("sqrt.c") 56) (insn 595 167 168 12 0x0 (set (reg:SI 0 r0 [115]) (reg/v:SI 4 r4 [82])) 6 {*movsi} (nil) (nil)) (insn 168 595 169 12 0x1002f450 (set (reg:SI 0 r0 [115]) (minus:SI (reg:SI 0 r0 [115]) (reg/v:SI 1 r1 [84]))) 13 {subsi3} (nil) (nil)) (insn 169 168 170 12 0x1002f450 (set (reg/v:SI 4 r4 [82]) (plus:SI (reg:SI 0 r0 [115]) (const_int 1 [0x1]))) 12 {addsi3} (insn_list 168 (nil)) (nil)) (note 170 169 171 12 ("sqrt.c") 57) (note 171 170 596 12 NOTE_INSN_DELETED) (insn 596 171 172 12 0x0 (set (reg:SI 0 r0 [116]) (reg/v:SI 1 r1 [84])) 6 {*movsi} (nil) (nil)) (insn 172 596 597 12 0x1002f450 (set (reg:SI 0 r0 [116]) (neg:SI (reg:SI 0 r0 [116]))) 15 {negsi2} (nil) (nil)) (insn 597 172 173 12 0x0 (set (reg:SI 2 r2) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 173 597 598 12 0x1002f450 (set (reg:SI 2 r2) (lshiftrt:SI (reg:SI 2 r2) (reg:SI 0 r0 [116]))) 24 {lshrsi3} (insn_list 172 (nil)) (nil)) (insn 598 173 174 12 0x0 (set (reg:SI 0 r0 [118]) (reg:SI 2 r2)) 6 {*movsi} (nil) (nil)) (insn 174 598 175 12 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ior:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [118]))) 26 {iorsi3} (insn_list 173 (nil)) (nil)) (note 175 174 176 12 ("sqrt.c") 58) (insn 176 175 177 12 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (reg/v:SI 1 r1 [84]))) 22 {ashlsi3} (nil) (nil)) ;; End of basic block 12, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 ;; Start of basic block 13, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (code_label 177 176 474 13 8 "" [1 uses]) (note 474 177 178 13 [bb 13] NOTE_INSN_BASIC_BLOCK) (note 178 474 179 13 ("sqrt.c") 60) (insn 179 178 180 13 0x1002f450 (set (reg/v:SI 4 r4 [82]) (plus:SI (reg/v:SI 4 r4 [82]) (const_int -1023 [0xfffffc01]))) 12 {addsi3} (nil) (nil)) (note 180 179 181 13 ("sqrt.c") 61) (insn 181 180 182 13 0x1002f450 (set (reg/v:SI 3 r3 [79]) (and:SI (reg/v:SI 3 r3 [79]) (const_int 1048575 [0xfffff]))) 25 {andsi3} (nil) (nil)) (insn 182 181 183 13 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ior:SI (reg/v:SI 3 r3 [79]) (const_int 1048576 [0x100000]))) 26 {iorsi3} (insn_list 181 (nil)) (nil)) (note 183 182 599 13 ("sqrt.c") 62) (insn 599 183 184 13 0x0 (set (reg:SI 0 r0 [120]) (reg/v:SI 4 r4 [82])) 6 {*movsi} (nil) (nil)) (insn 184 599 185 13 0x1002f450 (set (reg:SI 0 r0 [120]) (and:SI (reg:SI 0 r0 [120]) (const_int 1 [0x1]))) 25 {andsi3} (insn_list 179 (nil)) (nil)) (insn:QI 185 184 186 13 0x1002f450 (set (cc0) (compare:SI (reg:SI 0 r0 [120]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 184 (nil)) (nil)) (jump_insn 186 185 189 13 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 196) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 13, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 (note 189 186 475 ("sqrt.c") 64) ;; Start of basic block 14, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (note 475 189 190 14 [bb 14] NOTE_INSN_BASIC_BLOCK) (note 190 475 600 14 NOTE_INSN_DELETED) (insn 600 190 191 14 0x0 (set (reg:SI 0 r0 [122]) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 191 600 192 14 0x1002f450 (set (reg:SI 0 r0 [122]) (lshiftrt:SI (reg:SI 0 r0 [122]) (const_int 31 [0x1f]))) 24 {lshrsi3} (nil) (nil)) (insn 192 191 193 14 0x1002f450 (set (reg:SI 0 r0 [123]) (plus:SI (reg:SI 0 r0 [122]) (reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 191 (nil)) (nil)) (insn 193 192 194 14 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [123]))) 12 {addsi3} (insn_list 192 (nil)) (nil)) (note 194 193 195 14 ("sqrt.c") 65) (insn 195 194 196 14 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (const_int 1 [0x1]))) 22 {ashlsi3} (nil) (nil)) ;; End of basic block 14, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 ;; Start of basic block 15, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (code_label 196 195 476 15 18 "" [1 uses]) (note 476 196 197 15 [bb 15] NOTE_INSN_BASIC_BLOCK) (note 197 476 198 15 ("sqrt.c") 67) (insn 198 197 199 15 0x1002f450 (set (reg/v:SI 4 r4 [82]) (ashiftrt:SI (reg/v:SI 4 r4 [82]) (const_int 1 [0x1]))) 23 {ashrsi3} (nil) (nil)) (note 199 198 200 15 ("sqrt.c") 70) (note 200 199 601 15 NOTE_INSN_DELETED) (insn 601 200 201 15 0x0 (set (reg:SI 0 r0 [125]) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 201 601 202 15 0x1002f450 (set (reg:SI 0 r0 [125]) (lshiftrt:SI (reg:SI 0 r0 [125]) (const_int 31 [0x1f]))) 24 {lshrsi3} (nil) (nil)) (insn 202 201 203 15 0x1002f450 (set (reg:SI 0 r0 [126]) (plus:SI (reg:SI 0 r0 [125]) (reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 201 (nil)) (nil)) (insn 203 202 204 15 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [126]))) 12 {addsi3} (insn_list 202 (nil)) (nil)) (note 204 203 205 15 ("sqrt.c") 71) (insn 205 204 206 15 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (const_int 1 [0x1]))) 22 {ashlsi3} (nil) (nil)) (note 206 205 207 15 ("sqrt.c") 72) (insn 207 206 208 15 0x1002f450 (set (reg/v:SI 17 r17 [76]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (insn 208 207 209 15 0x1002f450 (set (reg/v:SI 15 r15 [80]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (insn 209 208 210 15 0x1002f450 (set (reg/v:SI 8 r8 [78]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (insn 210 209 211 15 0x1002f450 (set (reg/v:SI 6 r6 [81]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (note 211 210 212 15 ("sqrt.c") 73) (insn 212 211 213 15 0x1002f450 (set (reg/v:SI 13 r13 [74]) (const_int 2097152 [0x200000])) 6 {*movsi} (nil) (nil)) ;; End of basic block 15, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 (note 213 212 214 ("sqrt.c") 75) (note 214 213 248 NOTE_INSN_LOOP_BEG) ;; Start of basic block 16, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153 (code_label 248 214 477 16 23 "" [1 uses]) (note 477 248 224 16 [bb 16] NOTE_INSN_BASIC_BLOCK) (note 224 477 602 16 ("sqrt.c") 77) (insn 602 224 225 16 0x0 (set (reg/v:SI 2 r2 [83]) (reg/v:SI 15 r15 [80])) 6 {*movsi} (nil) (nil)) (insn 225 602 226 16 0x1002f450 (set (reg/v:SI 2 r2 [83]) (plus:SI (reg/v:SI 2 r2 [83]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) (note 226 225 227 16 ("sqrt.c") 78) (insn:QI 227 226 228 16 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 2 r2 [83]) (reg/v:SI 3 r3 [79]))) 29 {cmpsi_internal} (insn_list 225 (nil)) (nil)) (jump_insn 228 227 231 16 0x1002f450 (set (pc) (if_then_else (gt (cc0) (const_int 0 [0x0])) (label_ref 237) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 16, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 83 153 (note 231 228 478 ("sqrt.c") 80) ;; Start of basic block 17, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 81 82 83 153 (note 478 231 603 17 [bb 17] NOTE_INSN_BASIC_BLOCK) (insn 603 478 232 17 0x0 (set (reg/v:SI 15 r15 [80]) (reg/v:SI 2 r2 [83])) 6 {*movsi} (nil) (nil)) (insn 232 603 233 17 0x1002f450 (set (reg/v:SI 15 r15 [80]) (plus:SI (reg/v:SI 15 r15 [80]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) (note 233 232 234 17 ("sqrt.c") 81) (insn 234 233 235 17 0x1002f450 (set (reg/v:SI 3 r3 [79]) (minus:SI (reg/v:SI 3 r3 [79]) (reg/v:SI 2 r2 [83]))) 13 {subsi3} (nil) (nil)) (note 235 234 236 17 ("sqrt.c") 82) (insn 236 235 237 17 0x1002f450 (set (reg/v:SI 6 r6 [81]) (plus:SI (reg/v:SI 6 r6 [81]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) ;; End of basic block 17, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 ;; Start of basic block 18, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153 (code_label 237 236 479 18 22 "" [1 uses]) (note 479 237 238 18 [bb 18] NOTE_INSN_BASIC_BLOCK) (note 238 479 239 18 ("sqrt.c") 84) (note 239 238 604 18 NOTE_INSN_DELETED) (insn 604 239 240 18 0x0 (set (reg:SI 0 r0 [128]) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 240 604 241 18 0x1002f450 (set (reg:SI 0 r0 [128]) (lshiftrt:SI (reg:SI 0 r0 [128]) (const_int 31 [0x1f]))) 24 {lshrsi3} (nil) (nil)) (insn 241 240 242 18 0x1002f450 (set (reg:SI 0 r0 [129]) (plus:SI (reg:SI 0 r0 [128]) (reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 240 (nil)) (nil)) (insn 242 241 243 18 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [129]))) 12 {addsi3} (insn_list 241 (nil)) (nil)) (note 243 242 244 18 ("sqrt.c") 85) (insn 244 243 245 18 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (const_int 1 [0x1]))) 22 {ashlsi3} (nil) (nil)) (note 245 244 246 18 ("sqrt.c") 86) (insn 246 245 247 18 0x1002f450 (set (reg/v:SI 13 r13 [74]) (lshiftrt:SI (reg/v:SI 13 r13 [74]) (const_int 1 [0x1]))) 24 {lshrsi3} (nil) (nil)) (note 247 246 542 18 NOTE_INSN_LOOP_CONT) (note 542 247 216 18 NOTE_INSN_LOOP_VTOP) (insn:QI 216 542 217 18 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 13 r13 [74]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 246 (nil)) (nil)) (jump_insn 217 216 253 18 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 248) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 8900 [0x22c4]) (nil))) ;; End of basic block 18, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 (note 253 217 255 NOTE_INSN_LOOP_END) (note 255 253 483 ("sqrt.c") 89) ;; Start of basic block 19, registers live: 20 [r20] 21 [r21] 30 [r30] 76 77 78 79 80 81 82 153 (note 483 255 256 19 [bb 19] NOTE_INSN_BASIC_BLOCK) (insn 256 483 257 19 0x1002f450 (set (reg/v:SI 13 r13 [74]) (const_int -2147483648 [0x80000000])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int -2147483648 [0x80000000]) (nil))) (note 257 256 585 19 ("sqrt.c") 90) (insn 585 257 543 19 0x0 (set (reg/v:SI 0 r0 [73]) (const_int -2147483648 [0x80000000])) 6 {*movsi} (nil) (expr_list:REG_EQUIV (const_int -2147483648 [0x80000000]) (nil))) (insn:QI 543 585 544 19 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 0 r0 [73]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (nil) (expr_list:REG_EQUAL (compare:SI (const_int -2147483648 [0x80000000]) (const_int 0 [0x0])) (nil))) (jump_insn 544 543 258 19 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 545) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 3600 [0xe10]) (nil))) ;; End of basic block 19, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 (note 258 544 328 NOTE_INSN_LOOP_BEG) ;; Start of basic block 20, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153 (code_label 328 258 484 20 33 "" [1 uses]) (note 484 328 268 20 [bb 20] NOTE_INSN_BASIC_BLOCK) (note 268 484 605 20 ("sqrt.c") 92) (insn 605 268 269 20 0x0 (set (reg/v:SI 14 r14 [75]) (reg/v:SI 17 r17 [76])) 6 {*movsi} (nil) (nil)) (insn 269 605 270 20 0x1002f450 (set (reg/v:SI 14 r14 [75]) (plus:SI (reg/v:SI 14 r14 [75]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) (note 270 269 271 20 ("sqrt.c") 93) (insn 271 270 272 20 0x1002f450 (set (reg/v:SI 2 r2 [83]) (reg/v:SI 15 r15 [80])) 6 {*movsi} (nil) (nil)) (note 272 271 273 20 ("sqrt.c") 94) (insn:QI 273 272 274 20 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 2 r2 [83]) (reg/v:SI 3 r3 [79]))) 29 {cmpsi_internal} (insn_list 271 (nil)) (nil)) (jump_insn 274 273 485 20 0x1002f450 (set (pc) (if_then_else (lt (cc0) (const_int 0 [0x0])) (label_ref 290) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 20, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 ;; Start of basic block 21, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153 (note 485 274 606 21 [bb 21] NOTE_INSN_BASIC_BLOCK) (insn 606 485 562 21 0x0 (set (reg:SI 0 r0 [164]) (reg/v:SI 2 r2 [83])) 6 {*movsi} (nil) (nil)) (insn 562 606 607 21 0x1002f450 (set (reg:SI 0 r0 [164]) (xor:SI (reg:SI 0 r0 [164]) (reg/v:SI 3 r3 [79]))) 27 {xorsi3} (nil) (nil)) (insn 607 562 563 21 0x0 (set (reg:SI 1 r1 [168]) (reg:SI 0 r0 [164])) 6 {*movsi} (nil) (nil)) (insn 563 607 564 21 0x1002f450 (set (reg:SI 1 r1 [168]) (neg:SI (reg:SI 1 r1 [168]))) 15 {negsi2} (insn_list 562 (nil)) (nil)) (insn 564 563 565 21 0x1002f450 (set (reg:SI 1 r1 [168]) (ior:SI (reg:SI 1 r1 [168]) (reg:SI 0 r0 [164]))) 26 {iorsi3} (insn_list 563 (nil)) (nil)) (insn 565 564 566 21 0x1002f450 (set (reg:SI 1 r1 [168]) (not:SI (reg:SI 1 r1 [168]))) 28 {one_cmplsi2} (insn_list 564 (nil)) (nil)) (note 566 565 567 21 NOTE_INSN_DELETED) (insn 567 566 280 21 0x1002f450 (set (reg:SI 1 r1 [168]) (lshiftrt:SI (reg:SI 1 r1 [168]) (const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 565 (nil)) (nil)) (insn 280 567 281 21 0x1002f450 (set (reg:SI 0 r0 [131]) (const_int 0 [0x0])) 6 {*movsi} (nil) (nil)) (insn:QI 281 280 282 21 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 12 r12 [77]) (reg/v:SI 14 r14 [75]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 282 281 488 21 0x1002f450 (set (pc) (if_then_else (ltu (cc0) (const_int 0 [0x0])) (label_ref 284) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 21, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168 ;; Start of basic block 22, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153 168 (note 488 282 283 22 [bb 22] NOTE_INSN_BASIC_BLOCK) (insn 283 488 284 22 0x1002f450 (set (reg:SI 0 r0 [131]) (const_int 1 [0x1])) 6 {*movsi} (nil) (insn_list:REG_WAS_0 280 (expr_list:REG_EQUAL (const_int 1 [0x1]) (nil)))) ;; End of basic block 22, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168 ;; Start of basic block 23, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 131 153 168 (code_label 284 283 489 23 30 "" [1 uses]) (note 489 284 285 23 [bb 23] NOTE_INSN_BASIC_BLOCK) (insn 285 489 286 23 0x1002f450 (set (reg:SI 1 r1 [168]) (and:SI (reg:SI 1 r1 [168]) (reg:SI 0 r0 [131]))) 25 {andsi3} (nil) (nil)) (insn:QI 286 285 287 23 0x1002f450 (set (cc0) (compare:SI (reg:SI 1 r1 [168]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 285 (nil)) (nil)) (jump_insn 287 286 290 23 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 317) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 23, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 ;; Start of basic block 24, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 77 78 79 80 81 82 83 153 (code_label 290 287 491 24 28 "" [1 uses]) (note 491 290 293 24 [bb 24] NOTE_INSN_BASIC_BLOCK) (note 293 491 608 24 ("sqrt.c") 96) (insn 608 293 294 24 0x0 (set (reg/v:SI 17 r17 [76]) (reg/v:SI 14 r14 [75])) 6 {*movsi} (nil) (nil)) (insn 294 608 295 24 0x1002f450 (set (reg/v:SI 17 r17 [76]) (plus:SI (reg/v:SI 17 r17 [76]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) (note 295 294 609 24 ("sqrt.c") 97) (insn 609 295 296 24 0x0 (set (reg:SI 0 r0 [133]) (reg/v:SI 14 r14 [75])) 6 {*movsi} (nil) (nil)) (insn 296 609 297 24 0x1002f450 (set (reg:SI 0 r0 [133]) (and:SI (reg:SI 0 r0 [133]) (const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil) (nil)) (insn:QI 297 296 298 24 0x1002f450 (set (cc0) (compare:SI (reg:SI 0 r0 [133]) (const_int -2147483648 [0x80000000]))) 29 {cmpsi_internal} (insn_list 296 (nil)) (nil)) (jump_insn 298 297 492 24 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 304) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 7100 [0x1bbc]) (nil))) ;; End of basic block 24, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 ;; Start of basic block 25, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153 (note 492 298 610 25 [bb 25] NOTE_INSN_BASIC_BLOCK) (insn 610 492 299 25 0x0 (set (reg:SI 1 r1 [134]) (reg/v:SI 17 r17 [76])) 6 {*movsi} (nil) (nil)) (insn 299 610 611 25 0x1002f450 (set (reg:SI 1 r1 [134]) (and:SI (reg:SI 1 r1 [134]) (const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil) (nil)) (insn 611 299 568 25 0x0 (set (reg:SI 0 r0 [170]) (reg:SI 1 r1 [134])) 6 {*movsi} (nil) (nil)) (insn 568 611 569 25 0x1002f450 (set (reg:SI 0 r0 [170]) (neg:SI (reg:SI 0 r0 [170]))) 15 {negsi2} (insn_list 299 (nil)) (nil)) (insn 569 568 570 25 0x1002f450 (set (reg:SI 0 r0 [170]) (ior:SI (reg:SI 0 r0 [170]) (reg:SI 1 r1 [134]))) 26 {iorsi3} (insn_list 568 (nil)) (nil)) (insn 570 569 571 25 0x1002f450 (set (reg:SI 0 r0 [170]) (not:SI (reg:SI 0 r0 [170]))) 28 {one_cmplsi2} (insn_list 569 (nil)) (nil)) (insn 571 570 573 25 0x1002f450 (set (reg:SI 0 r0 [170]) (lshiftrt:SI (reg:SI 0 r0 [170]) (const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 570 (nil)) (nil)) (insn 573 571 302 25 0x1002f450 (set (reg/v:SI 15 r15 [80]) (plus:SI (reg/v:SI 15 r15 [80]) (reg:SI 0 r0 [170]))) 12 {addsi3} (insn_list 571 (nil)) (nil)) ;; End of basic block 25, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 (note 302 573 304 ("sqrt.c") 98) ;; Start of basic block 26, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153 (code_label 304 302 494 26 31 "" [1 uses]) (note 494 304 305 26 [bb 26] NOTE_INSN_BASIC_BLOCK) (note 305 494 306 26 ("sqrt.c") 99) (insn 306 305 307 26 0x1002f450 (set (reg/v:SI 3 r3 [79]) (minus:SI (reg/v:SI 3 r3 [79]) (reg/v:SI 2 r2 [83]))) 13 {subsi3} (nil) (nil)) (note 307 306 308 26 ("sqrt.c") 100) (insn:QI 308 307 309 26 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 12 r12 [77]) (reg/v:SI 14 r14 [75]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 309 308 310 26 0x1002f450 (set (pc) (if_then_else (geu (cc0) (const_int 0 [0x0])) (label_ref 312) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 26, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153 (note 310 309 495 ("sqrt.c") 101) ;; Start of basic block 27, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 153 (note 495 310 311 27 [bb 27] NOTE_INSN_BASIC_BLOCK) (insn 311 495 312 27 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (const_int -1 [0xffffffff]))) 12 {addsi3} (nil) (nil)) ;; End of basic block 27, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153 ;; Start of basic block 28, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 153 (code_label 312 311 496 28 32 "" [1 uses]) (note 496 312 313 28 [bb 28] NOTE_INSN_BASIC_BLOCK) (note 313 496 314 28 ("sqrt.c") 102) (insn 314 313 315 28 0x1002f450 (set (reg/v:SI 12 r12 [77]) (minus:SI (reg/v:SI 12 r12 [77]) (reg/v:SI 14 r14 [75]))) 13 {subsi3} (nil) (nil)) (note 315 314 316 28 ("sqrt.c") 103) (insn 316 315 317 28 0x1002f450 (set (reg/v:SI 8 r8 [78]) (plus:SI (reg/v:SI 8 r8 [78]) (reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil) (nil)) ;; End of basic block 28, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 ;; Start of basic block 29, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153 (code_label 317 316 497 29 27 "" [1 uses]) (note 497 317 318 29 [bb 29] NOTE_INSN_BASIC_BLOCK) (note 318 497 319 29 ("sqrt.c") 105) (note 319 318 612 29 NOTE_INSN_DELETED) (insn 612 319 320 29 0x0 (set (reg:SI 0 r0 [136]) (reg/v:SI 12 r12 [77])) 6 {*movsi} (nil) (nil)) (insn 320 612 321 29 0x1002f450 (set (reg:SI 0 r0 [136]) (lshiftrt:SI (reg:SI 0 r0 [136]) (const_int 31 [0x1f]))) 24 {lshrsi3} (nil) (nil)) (insn 321 320 322 29 0x1002f450 (set (reg:SI 0 r0 [137]) (plus:SI (reg:SI 0 r0 [136]) (reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 320 (nil)) (nil)) (insn 322 321 323 29 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (reg:SI 0 r0 [137]))) 12 {addsi3} (insn_list 321 (nil)) (nil)) (note 323 322 324 29 ("sqrt.c") 106) (insn 324 323 325 29 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ashift:SI (reg/v:SI 12 r12 [77]) (const_int 1 [0x1]))) 22 {ashlsi3} (nil) (nil)) (note 325 324 326 29 ("sqrt.c") 107) (insn 326 325 327 29 0x1002f450 (set (reg/v:SI 13 r13 [74]) (lshiftrt:SI (reg/v:SI 13 r13 [74]) (const_int 1 [0x1]))) 24 {lshrsi3} (nil) (nil)) (note 327 326 549 29 NOTE_INSN_LOOP_CONT) (note 549 327 260 29 NOTE_INSN_LOOP_VTOP) (insn:QI 260 549 261 29 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 13 r13 [74]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 326 (nil)) (nil)) (jump_insn 261 260 333 29 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 328) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 8900 [0x22c4]) (nil))) ;; End of basic block 29, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153 (note 333 261 545 NOTE_INSN_LOOP_END) ;; Start of basic block 30, registers live: 20 [r20] 21 [r21] 30 [r30] 77 78 79 81 82 153 (code_label 545 333 501 30 52 "" [1 uses]) (note 501 545 335 30 [bb 30] NOTE_INSN_BASIC_BLOCK) (note 335 501 336 30 ("sqrt.c") 111) (insn 336 335 337 30 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ior:SI (reg/v:SI 3 r3 [79]) (reg/v:SI 12 r12 [77]))) 26 {iorsi3} (nil) (nil)) (insn:QI 337 336 338 30 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 3 r3 [79]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 336 (nil)) (nil)) (jump_insn 338 337 341 30 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 408) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 30, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153 (note 341 338 502 ("sqrt.c") 113) ;; Start of basic block 31, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153 (note 502 341 342 31 [bb 31] NOTE_INSN_BASIC_BLOCK) (insn 342 502 343 31 0x1002f450 (set (reg/v:DF 10 r10 [72]) (mem/u/f:DF (symbol_ref/u:SI ("*.LC0")) [2 S8 A32])) 10 {*movdf} (nil) (expr_list:REG_EQUIV (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1]) (nil))) (note 343 342 344 31 ("sqrt.c") 114) (note 344 343 345 31 NOTE_INSN_DELETED) (insn 345 344 349 31 0x1002f450 (set (reg:DF 17 r17) (reg/v:DF 10 r10 [72])) 10 {*movdf} (insn_list 342 (nil)) (expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1]) (nil))) (insn 349 345 350 31 0x1002f450 (set (reg:SI 19 r19) (const_int 0 [0x0])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (insn 350 349 351 31 0x1002f450 (set (reg:SI 0 r0) (const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000]) (nil))) (call_insn/u 351 350 352 31 0x1002f450 (parallel [ (set (reg:SI 18 r18) (call (mem:QI (symbol_ref:SI ("__gedf2")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 350 (insn_list 349 (insn_list 345 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 352 351 353 31 0x1002f450 (set (reg:SI 18 r18 [143]) (reg:SI 18 r18)) 6 {*movsi} (insn_list 351 (nil)) (expr_list:REG_EQUAL (expr_list (reg/f:SI 139) (expr_list (reg/v:DF 10 r10 [72]) (expr_list (reg/v:DF 10 r10 [72]) (nil)))) (nil))) (insn:QI 353 352 354 31 0x1002f450 (set (cc0) (compare:SI (reg:SI 18 r18 [143]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 352 (nil)) (nil)) (jump_insn 354 353 360 31 0x1002f450 (set (pc) (if_then_else (lt (cc0) (const_int 0 [0x0])) (label_ref 408) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 2100 [0x834]) (nil))) ;; End of basic block 31, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153 (note 360 354 362 ("sqrt.c") 116) (note 362 360 504 ("sqrt.c") 117) ;; Start of basic block 32, registers live: 20 [r20] 21 [r21] 30 [r30] 72 78 81 82 153 (note 504 362 363 32 [bb 32] NOTE_INSN_BASIC_BLOCK) (insn:QI 363 504 364 32 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 8 r8 [78]) (const_int -1 [0xffffffff]))) 29 {cmpsi_internal} (nil) (nil)) (jump_insn 364 363 367 32 0x1002f450 (set (pc) (if_then_else (ne (cc0) (const_int 0 [0x0])) (label_ref 373) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 7100 [0x1bbc]) (nil))) ;; End of basic block 32, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153 (note 367 364 505 ("sqrt.c") 119) ;; Start of basic block 33, registers live: 20 [r20] 21 [r21] 30 [r30] 81 82 153 (note 505 367 368 33 [bb 33] NOTE_INSN_BASIC_BLOCK) (insn 368 505 369 33 0x1002f450 (set (reg/v:SI 8 r8 [78]) (const_int 0 [0x0])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (note 369 368 370 33 ("sqrt.c") 120) (insn 370 369 371 33 0x1002f450 (set (reg/v:SI 6 r6 [81]) (plus:SI (reg/v:SI 6 r6 [81]) (const_int 1 [0x1]))) 12 {addsi3} (nil) (nil)) (jump_insn 371 370 372 33 0x1002f450 (set (pc) (label_ref 408)) 35 {jump} (nil) (nil)) ;; End of basic block 33, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153 (barrier 372 371 373) ;; Start of basic block 34, registers live: 20 [r20] 21 [r21] 30 [r30] 72 78 81 82 153 (code_label 373 372 506 34 37 "" [1 uses]) (note 506 373 374 34 [bb 34] NOTE_INSN_BASIC_BLOCK) (note 374 506 375 34 ("sqrt.c") 122) (note 375 374 376 34 NOTE_INSN_DELETED) (insn 376 375 380 34 0x1002f450 (set (reg:DF 17 r17) (reg/v:DF 10 r10 [72])) 10 {*movdf} (nil) (expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1]) (nil))) (insn 380 376 381 34 0x1002f450 (set (reg:SI 19 r19) (const_int 0 [0x0])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (insn 381 380 382 34 0x1002f450 (set (reg:SI 0 r0) (const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000]) (nil))) (call_insn/u 382 381 383 34 0x1002f450 (parallel [ (set (reg:SI 18 r18) (call (mem:QI (symbol_ref:SI ("__gtdf2")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 381 (insn_list 380 (insn_list 376 (nil)))) (expr_list:REG_EH_REGION (const_int -1 [0xffffffff]) (nil)) (expr_list (use (reg:SI 0 r0)) (expr_list (use (reg:SI 19 r19)) (expr_list (use (reg:DF 17 r17)) (nil))))) (insn 383 382 384 34 0x1002f450 (set (reg:SI 18 r18 [148]) (reg:SI 18 r18)) 6 {*movsi} (insn_list 382 (nil)) (expr_list:REG_EQUAL (expr_list (reg/f:SI 144) (expr_list (reg/v:DF 10 r10 [72]) (expr_list (reg/v:DF 10 r10 [72]) (nil)))) (nil))) (insn:QI 384 383 385 34 0x1002f450 (set (cc0) (compare:SI (reg:SI 18 r18 [148]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 383 (nil)) (nil)) (jump_insn 385 384 391 34 0x1002f450 (set (pc) (if_then_else (le (cc0) (const_int 0 [0x0])) (label_ref 401) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 2100 [0x834]) (nil))) ;; End of basic block 34, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153 (note 391 385 508 ("sqrt.c") 124) ;; Start of basic block 35, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153 (note 508 391 613 35 [bb 35] NOTE_INSN_BASIC_BLOCK) (insn 613 508 574 35 0x0 (set (reg:SI 1 r1 [176]) (reg/v:SI 8 r8 [78])) 6 {*movsi} (nil) (nil)) (insn 574 613 614 35 0x1002f450 (set (reg:SI 1 r1 [176]) (xor:SI (reg:SI 1 r1 [176]) (const_int -2 [0xfffffffe]))) 27 {xorsi3} (nil) (nil)) (insn 614 574 575 35 0x0 (set (reg:SI 0 r0 [177]) (reg:SI 1 r1 [176])) 6 {*movsi} (nil) (nil)) (insn 575 614 576 35 0x1002f450 (set (reg:SI 0 r0 [177]) (neg:SI (reg:SI 0 r0 [177]))) 15 {negsi2} (insn_list 574 (nil)) (nil)) (insn 576 575 577 35 0x1002f450 (set (reg:SI 0 r0 [177]) (ior:SI (reg:SI 0 r0 [177]) (reg:SI 1 r1 [176]))) 26 {iorsi3} (insn_list 575 (nil)) (nil)) (insn 577 576 578 35 0x1002f450 (set (reg:SI 0 r0 [177]) (not:SI (reg:SI 0 r0 [177]))) 28 {one_cmplsi2} (insn_list 576 (nil)) (nil)) (insn 578 577 580 35 0x1002f450 (set (reg:SI 0 r0 [177]) (lshiftrt:SI (reg:SI 0 r0 [177]) (const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 577 (nil)) (nil)) (insn 580 578 394 35 0x1002f450 (set (reg/v:SI 6 r6 [81]) (plus:SI (reg/v:SI 6 r6 [81]) (reg:SI 0 r0 [177]))) 12 {addsi3} (insn_list 578 (nil)) (nil)) (note 394 580 397 35 ("sqrt.c") 125) (note 397 394 398 35 ("sqrt.c") 126) (insn 398 397 399 35 0x1002f450 (set (reg/v:SI 8 r8 [78]) (plus:SI (reg/v:SI 8 r8 [78]) (const_int 2 [0x2]))) 12 {addsi3} (nil) (nil)) (jump_insn 399 398 400 35 0x1002f450 (set (pc) (label_ref 408)) 35 {jump} (nil) (nil)) ;; End of basic block 35, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153 (barrier 400 399 401) ;; Start of basic block 36, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153 (code_label 401 400 511 36 39 "" [1 uses]) (note 511 401 402 36 [bb 36] NOTE_INSN_BASIC_BLOCK) (note 402 511 615 36 ("sqrt.c") 129) (insn 615 402 403 36 0x0 (set (reg:SI 0 r0 [149]) (reg/v:SI 8 r8 [78])) 6 {*movsi} (nil) (nil)) (insn 403 615 404 36 0x1002f450 (set (reg:SI 0 r0 [149]) (and:SI (reg:SI 0 r0 [149]) (const_int 1 [0x1]))) 25 {andsi3} (nil) (nil)) (insn 404 403 408 36 0x1002f450 (set (reg/v:SI 8 r8 [78]) (plus:SI (reg/v:SI 8 r8 [78]) (reg:SI 0 r0 [149]))) 12 {addsi3} (insn_list 403 (nil)) (nil)) ;; End of basic block 36, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153 ;; Start of basic block 37, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153 (code_label 408 404 515 37 34 "" [4 uses]) (note 515 408 409 37 [bb 37] NOTE_INSN_BASIC_BLOCK) (note 409 515 616 37 ("sqrt.c") 132) (insn 616 409 410 37 0x0 (set (reg/v:SI 3 r3 [79]) (reg/v:SI 6 r6 [81])) 6 {*movsi} (nil) (nil)) (insn 410 616 411 37 0x1002f450 (set (reg/v:SI 3 r3 [79]) (ashiftrt:SI (reg/v:SI 3 r3 [79]) (const_int 1 [0x1]))) 23 {ashrsi3} (nil) (nil)) (insn 411 410 412 37 0x1002f450 (set (reg/v:SI 3 r3 [79]) (plus:SI (reg/v:SI 3 r3 [79]) (const_int 1071644672 [0x3fe00000]))) 12 {addsi3} (insn_list 410 (nil)) (nil)) (note 412 411 617 37 ("sqrt.c") 133) (insn 617 412 413 37 0x0 (set (reg/v:SI 12 r12 [77]) (reg/v:SI 8 r8 [78])) 6 {*movsi} (nil) (nil)) (insn 413 617 414 37 0x1002f450 (set (reg/v:SI 12 r12 [77]) (lshiftrt:SI (reg/v:SI 12 r12 [77]) (const_int 1 [0x1]))) 24 {lshrsi3} (nil) (nil)) (note 414 413 415 37 ("sqrt.c") 134) (insn 415 414 416 37 0x1002f450 (set (reg/v:SI 6 r6 [81]) (and:SI (reg/v:SI 6 r6 [81]) (const_int 1 [0x1]))) 25 {andsi3} (nil) (nil)) (insn:QI 416 415 417 37 0x1002f450 (set (cc0) (compare:SI (reg/v:SI 6 r6 [81]) (const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 415 (nil)) (nil)) (jump_insn 417 416 418 37 0x1002f450 (set (pc) (if_then_else (eq (cc0) (const_int 0 [0x0])) (label_ref 420) (pc))) 31 {branch_internal} (nil) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil))) ;; End of basic block 37, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 (note 418 417 516 ("sqrt.c") 135) ;; Start of basic block 38, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (note 516 418 419 38 [bb 38] NOTE_INSN_BASIC_BLOCK) (insn 419 516 420 38 0x1002f450 (set (reg/v:SI 12 r12 [77]) (ior:SI (reg/v:SI 12 r12 [77]) (const_int -2147483648 [0x80000000]))) 26 {iorsi3} (nil) (nil)) ;; End of basic block 38, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153 ;; Start of basic block 39, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153 (code_label 420 419 517 39 43 "" [1 uses]) (note 517 420 421 39 [bb 39] NOTE_INSN_BASIC_BLOCK) (note 421 517 422 39 ("sqrt.c") 136) (insn 422 421 423 39 0x1002f450 (set (reg/v:SI 4 r4 [82]) (ashift:SI (reg/v:SI 4 r4 [82]) (const_int 20 [0x14]))) 22 {ashlsi3} (nil) (nil)) (note 423 422 427 39 NOTE_INSN_DELETED) (note 427 423 428 39 ("sqrt.c") 139) (note 428 427 429 39 ("sqrt.c") 140) (insn 429 428 618 39 0x1002f420 (set (reg/v:SI 4 r4 [82]) (plus:SI (reg/v:SI 4 r4 [82]) (reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 422 (nil)) (nil)) (insn 618 429 619 39 0x0 (set (reg:SI 0 r0) (reg/v:SI 4 r4 [82])) 6 {*movsi} (nil) (nil)) (insn 619 618 430 39 0x0 (set (mem:SI (plus:SI (reg/f:SI 21 r21) (const_int -4 [0xfffffffc])) [3 iw_u S4 A32]) (reg:SI 0 r0)) 6 {*movsi} (nil) (nil)) (note 430 619 431 39 ("sqrt.c") 141) (insn 431 430 620 39 0x1002f420 (set (reg:SI 0 r0) (reg/v:SI 12 r12 [77])) 6 {*movsi} (insn_list 429 (nil)) (nil)) (insn 620 431 621 39 0x0 (set (reg:DI 2 r2) (reg:DI 0 r0)) 7 {*movdi} (nil) (nil)) (insn 621 620 432 39 0x0 (set (mem:DI (plus:SI (reg/f:SI 21 r21) (const_int -8 [0xfffffff8])) [3 iw_u S8 A32]) (reg:DI 2 r2)) 7 {*movdi} (nil) (nil)) (note 432 621 433 39 ("sqrt.c") 142) (insn 433 432 436 39 0x1002f420 (set (reg:DF 14 r14 [70]) (reg:DF 0 r0)) 10 {*movdf} (insn_list 431 (nil)) (nil)) (note 436 433 443 39 ("sqrt.c") 145) ;; End of basic block 39, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 (note 443 436 444 NOTE_INSN_FUNCTION_END) (note 444 443 445 ("sqrt.c") 146) ;; Start of basic block 40, registers live: 20 [r20] 21 [r21] 30 [r30] 70 (code_label 445 444 520 40 1 "" [3 uses]) (note 520 445 446 40 [bb 40] NOTE_INSN_BASIC_BLOCK) (insn 446 520 449 40 0x1002f480 (set (reg/i:DF 18 r18) (reg:DF 14 r14 [70])) 10 {*movdf} (nil) (nil)) (insn 449 446 586 40 0x1002f480 (use (reg/i:DF 18 r18)) -1 (insn_list 446 (nil)) (nil)) ;; End of basic block 40, registers live: 18 [r18] 19 [r19] 20 [r20] 21 [r21] 30 [r30] 64 [ap] (note 586 449 0 NOTE_INSN_DELETED) ;; Function main ;; 0 regs to allocate: ;; 73 conflicts: 73 18 19 20 30 Spilling for insn 13. Reloads for insn # 13 Reload 0: ADDR32_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), optional, can't combine, secondary_reload_p Reload 1: reload_out (DF) = (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32]) NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional reload_out_reg: (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32]) secondary_out_reload = 0 ;; Register dispositions: 73 in 18 ;; Hard regs used: 16 17 18 19 21 64 (note 1 0 3 ("sqrt.c") 151) (note 3 1 7 NOTE_INSN_FUNCTION_BEG) (note 7 3 27 ("sqrt.c") 152) ;; Start of basic block 0, registers live: 20 [r20] 21 [r21] 30 [r30] (note 27 7 9 0 [bb 0] NOTE_INSN_BASIC_BLOCK) (note 9 27 10 0 NOTE_INSN_DELETED) (insn 10 9 11 0 0x0 (set (reg:DF 17 r17) (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])) 10 {*movdf} (insn_list 8 (nil)) (nil)) (call_insn 11 10 12 0 0x0 (parallel [ (set (reg:DF 18 r18) (call (mem:QI (symbol_ref:SI ("__ieee754_sqrt")) [0 S1 A8]) (const_int 0 [0x0]))) (use (const_int 0 [0x0])) (clobber (reg:SI 16 r16)) ]) 33 {call_value_internal} (insn_list 10 (nil)) (expr_list:REG_EH_REGION (const_int 0 [0x0]) (nil)) (expr_list (use (reg:DF 17 r17)) (nil))) (insn 12 11 13 0 0x0 (set (reg:DF 18 r18 [73]) (reg:DF 18 r18)) 10 {*movdf} (insn_list 11 (nil)) (expr_list:REG_EQUIV (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32]) (nil))) (insn 13 12 14 0 0x0 (set (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32]) (reg:DF 18 r18 [73])) 10 {*movdf} (insn_list 12 (nil)) (nil)) (note 14 13 20 0 ("sqrt.c") 154) (note 20 14 21 0 NOTE_INSN_FUNCTION_END) (note 21 20 23 0 ("sqrt.c") 155) (insn 23 21 26 0 0x0 (set (reg/i:SI 18 r18) (const_int 0 [0x0])) 6 {*movsi} (nil) (expr_list:REG_EQUAL (const_int 0 [0x0]) (nil))) (insn 26 23 30 0 0x0 (use (reg/i:SI 18 r18)) -1 (insn_list 23 (nil)) (nil)) ;; End of basic block 0, registers live: 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] (note 30 26 0 NOTE_INSN_DELETED)