A constant pool and addressing mode question

["Ling-hua Tseng" <uranus at it dot muds dot net>]

I'm porting GCC 4.0.1 to a new architecture.
Its load/store instructions are similar to ARM's.

The RTL is always generating a symbol_ref RTX to access a global variable,
and the symbol_ref is an immediate which will be determined at the assembling/linking time.
The addressing modes of my architecture didn't support the "direct addressing mode",
that is, the syntax "load    <reg>, <symbol name>" isn't allowed.
I can only use the the two forms:
   "load    <reg0>, <reg1>[#<immed>]" and
   "load    <reg0>, <reg1>[<reg2>]".

I cannot generate the following instructions if I have limited length of immediate field:
   mov    <reg0>, <symbol name>
   load    <reg1>, <reg0>[#0]

I noticed that the ARM's porting used the hook "TARGET_MACHINE_DEPENDENT_REORG" to solve it.
It generated a "mini constant pool" in the proper location by computing the insn length attributes,
and replaced the "ldr    <reg>, <symbol name>" to "ldr    <reg>, <label name of mini constant pool element>".
The mini constant pool looks like:
.L3:
       .word    <symbol name 1>
.L4:
       .word    <symbol name 2>
...

And I has found the comment which is just before the implementation of the hook for a long time:
/* Gcc puts the pool in the wrong place for ARM, since we can only
  load addresses a limited distance around the pc.  We do some 
  special munging to move the constant pool values to the correct
  point in the code.  */

In my porting, I have no idea to let GCC to generate the constant pool with symbol names if I don't use
the TARGET_MACHINE_DEPENDENT_REORG hook.
(Currently, there are only string literal constant pools appeared in my porting.)
So I cannot understand what the comment "Gcc puts the pool in the wrong place for ARM" means.

I have three questions:
   1. Could GCC generate the kind of constant pools which are contained symbol names by setting some
       target machine macros? (even if it was broken)
   2. Are there any general soultions by telling GCC how far the load/store instruction could access?
   3. In order to reduce the memory accessing operations, I want to use some special assmebly code syntax:
                   movim    r1, <symbol name>/highpart    @ move MSB 16-bit of the symbol address to r1 [31..16]
                   movil      r1, <symbol name>/lowpart     @ move LSB 16-bit of the symbol address to r1 [15..0]
       instead of the ARM's solution:
                   ldr          r1,  .L3
                   ...
           .L3:
                   .word     <symbol name>
       Of course it should to modify the assembler/linker and loader.
       Is it a good idea?

Thanks a lot.