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Re: The VLIW bundle output questions
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: Ling-hua Tseng <uranus at it dot muds dot net>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 19 May 2005 17:24:29 -0400
- Subject: Re: The VLIW bundle output questions
- References: <000501c55cad$3c934830$0201a8c0@uranus>
Ling-hua Tseng wrote:
>
> For example:
> ===================================[top]====================================
> mov .risc0 r1, #25 \\
> ldw .risc0 r2, [fp, #30] \\
> addub .mac0 d0, d4, d3 \\
> subub .mac1 d11, d7, d4
> add .risc0 r3, r1, r5
> ===================================[end]====================================
> (The symbol "\\" means "parallel". The next instruction will be issued
> at the same cycle.)
> The first 4 instructions are in the same VLIW bundle (issued in the
> first cycle),
> and the last one instruction is in other VLIW bundle (issued in the
> next cycle).
>
> I plan to schedule the instructions by the "pipeline description".
> Currently I have three questions after I reading the Ch10 ~ 13 of GCC
> internals manual:
> (1) How can I output the parallel symbol "\\" in the final pass?
> It's obvious that I should append the "\\" to some instructions which
> are in the same bundle,
> but I didn't find out the corresponding target machine macros/hooks to
> do so.
I'd recommend to look at FRV port as a possible solution (e.g. FRV insns
have an assembler packing suffix '.p' which is analog for \\ in your port).
You can also find answers for the other questions in this port because
FRV is VLIW processor too.
Vlad