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RE: Store scheduling with DFA scheduler
- From: Richard Earnshaw <rearnsha at gcc dot gnu dot org>
- To: Jon Beniston <jon at beniston dot com>
- Cc: "'Nathan Sidwell'" <nathan at codesourcery dot com>, gcc at gcc dot gnu dot org
- Date: Tue, 26 Apr 2005 13:43:56 +0100
- Subject: RE: Store scheduling with DFA scheduler
- Organization: GNU
- References: <200504261154.j3QBsJuF003562@mx0.arm.com>
On Tue, 2005-04-26 at 12:52, Jon Beniston wrote:
> > Jon,
> > > (define_insn_reservation "arith" 1 (eq_attr "type" "arith") "x")
> > > (define_insn_reservation "loads" 2 (eq_attr "type" "load") "x,m")
> > > (define_insn_reservation "stores" 3 (eq_attr "type"
> > "store") "x,m*2")
> > Stores don't really have a 'result', why have you set the
> > cycle count to 3? Shouldn't it be '1'? (then you won't need
> > store bypasses for autoincrements)
> Primilary because that's how it appears to be coded in the ARM port (e.g
> store_wbuf in arm-generic.md). I had tried both ways though, and for this
> particular problem, changing this value appears to have no effect. I can see
> that it would for autoinc though.
The store_wbuf code always was a little suspect, even in the days before
the DFA scheduler. These days it's only used for cores that have no
other scheduling constraints.