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Re: Question about instruction packing
_On 05-Jan-2005 16:15, Steven Bosscher san wrote_:
On Wednesday 05 January 2005 06:43, Balaji S wrote:
After solving that, now i have a different problem with packing that two
insns of two word each are getting packed together. Do i need to control
this using TARGET_SCHED_VARIABLE_ISSUE?. If not, please guide me to specify
this in DFA description itself.
You probably need to set some attribute on the insns and say that
the pipe is full if a two-word insns is issued. m32r does that
too ;-)
(define_insn_reservation "ic3_all" 1
(eq_attr "length" "2")
"ic3_slot0+ic3_slot1")
(define_insn "*addhi3"
[(set (match_operand:HI 0 "register_operand" "=e,e")
(plus:HI (match_operand:HI 1 "register_operand" "%e,e")
(match_operand:HI 2 " nonmemory_operand" "e,i")))]
""
"@add %0, %1, %2
addi %0, %1, %2"
[(set_attr "length" "1,2")
(set_attr "type" "arith,arith")])
m/c desc. already have the above DFA desc. and insn. Hope they are enough to convey my intention.