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Re: discouraging register use


Do I have to do something like this?  If so, I'm going to have some
*really* long lines in my md file (for this chip).  Or is there some
other way of changing gcc's register preferences, without precluding
the registers completely?

Of course there is CLASS_LIKELY_SPILLED_P and CANNOT_CHANGE_MODE_CLASS, but that would be lying to the compiler.

  [(set (match_operand:SI 0 "" "c,c,?m,?m")
        (plus:SI (match_operand:SI 1 "" "0,0,0,0")
		 (match_operand:SI 1 "" "c,?m,c,?m")))]


If the read-modify-write operand has double cost for the memory access, it should be more like:

 [(set (match_operand:SI 0 "" "c,c,??m,??m")
       (plus:SI (match_operand:SI 1 "" "0,0,0,0")
		 (match_operand:SI 1 "" "c,?m,c,?m")))]

Also, you can tweak the cost of the alternatives with the expensive class by adding
some more '?'s.

To allow realod inheritance to work where the same value happens to lie around in a 'c'
class register, you also have to extend all the 'm' alternatives with a 'c':
 [(set (match_operand:SI 0 "" "c,c,??mc,??mc")
       (plus:SI (match_operand:SI 1 "" "0,0,0,0")
		 (match_operand:SI 1 "" "c,?mc,c,?mc")))]
and make sure the union of the two classes is a register class.

Another thing to consider is if you want register class preferencing to ignore or further
penalize the 'm' class.
E.g. this would triple the penalty for register preferencing:
 [(set (match_operand:SI 0 "" "c,c,??mc#????,??mc#????")
       (plus:SI (match_operand:SI 1 "" "0,0,0,0")
		 (match_operand:SI 1 "" "c,?mc#??,c,?mc#??")))]

And this ignores the 'm'; class alternatives for preferencing:
 [(set (match_operand:SI 0 "" "c,c,??*mc,??*mc")
       (plus:SI (match_operand:SI 1 "" "0,0,0,0")
		 (match_operand:SI 1 "" "c,?*mc,c,?*mc")))]


You might also consider making your addsi commutative, i.e. adding a '%' constraint modifier.



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