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Re: Question about instruction packing
- From: Steven Bosscher <stevenb at suse dot de>
- To: gcc at gcc dot gnu dot org
- Cc: Balaji S <sivanbalaji at acmet dot com>
- Date: Mon, 3 Jan 2005 08:54:40 +0100
- Subject: Re: Question about instruction packing
- Organization: SUSE Labs
- References: <41D8EA86.firstname.lastname@example.org>
On Monday 03 January 2005 07:47, Balaji S wrote:
> Hi all,
> I am working on a DSP processor which can issue two instructions, each one
> word, in one cycle.
> The following is the DFA description for the above behavior.
> (define_automaton "ic3")
> (define_cpu_unit "ic3_slot0, ic3_slot1" "ic3")
> (define_insn_reservation "ic3_any" 1
> (eq_attr "length" "1")
> (define_insn_reservation "ic3_all" 1
> (eq_attr "length" "2")
> With the above descriptions the instructions are getting rearranged but the
> packing info, *TImode for insn*, is not available. Please correct me if any
> mistakes in descriptions and guide me to get the packing info in insns.
Looks very similar to m32r. Look at the DFA description for
that target, maybe there's something useful to learn for you