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Question about instruction packing
- From: Balaji S <sivanbalaji at acmet dot com>
- To: gcc at gcc dot gnu dot org
- Date: Mon, 03 Jan 2005 12:17:34 +0530
- Subject: Question about instruction packing
- Organization: Acme Technologies Pvt. Ltd.
I am working on a DSP processor which can issue two instructions, each one word, in one cycle.
The following is the DFA description for the above behavior.
(define_cpu_unit "ic3_slot0, ic3_slot1" "ic3")
(define_insn_reservation "ic3_any" 1
(eq_attr "length" "1")
(define_insn_reservation "ic3_all" 1
(eq_attr "length" "2")
With the above descriptions the instructions are getting rearranged but the packing info, *TImode for insn*, is not available. Please correct me if any mistakes in descriptions and guide me to get the packing info in insns.
Thanks in advance.