Re: Help with constraint for single register

[Robert Baruch <autophile at gmail dot com>]

On Mon, 27 Dec 2004 12:39:53 -0500, Daniel Jacobowitz <drow@false.org> wrote:
> On Sun, Dec 26, 2004 at 07:26:21PM -0500, Robert Baruch wrote:
> > Well, I'm afraid I'm very confused about the whole reload thing. I defined:
> >
> > #define PREFERRED_RELOAD_CLASS(X,CLASS) \
> >   ((REG_P(X) && REGNO(X)==W_REGNO) ? (CLASS) : W_REG)
> > #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) W_REG
> >
> > So if I understand the documentation correctly, this says that:
> >
> > 1) W may be moved into any register
> > 2) Any register except W must be moved into W
> > 3) All moves must involve the W register as an intermediate register
> 
> Take a look at Ulrich's suggestion again, and some other port that uses
> SECONDARY_RELOAD_CLASS.  You can't ignore the arguments that way;
> sometimes it has to return NO_REGS.

Ohhh... OK. I redefined SECONDARY_RELOAD_CLASS to:

#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
	( ((CLASS)==W_REG || (REG_P(X) && REGNO(X)==W_REGNO)) ? NO_REGS : W_REG )

So now it reads, use the W register for all cases not involving W,
otherwise no scratch register is necessary (because the scratch
register would be W anyway).

That seems to get me a little further along.

Believe me, I am trying to understand the other ports, its just that
I'm only familiar with the i386 processor (not even the 486 et al).
Also the Z80, but I don't see a port for that one... A lot of the
stuff in the ports is opaque to me until I have it explained :)


> > 1) Generate only moves through W in the expander for movqi.
> 
> You want to do this, because you'll get better code that way.
> 
> > 2) Define the reload classes appropriately so that reloads always go through W.
> 
> Probably, yes.

OK, that's all done... except now the next problem is that it looks
like the GCSE phase incorrectly eliminated a move involving W.

In this architecture, putting an address in the FSR register will
cause the INDF register to be aliased to that address. That's the only
way you can do indirect addressing on this processor. During the CSE
phase, I had these insns. This sequence takes a value from the TMP
register, and stores it into the location pointed to by pseudo-59,
i.e. (P59) <- TMP:

2618: W <- pseudo-59
2619: clobber INDF
2620: FSR <- W
2621: use FSR
2622: W <- TMP
2623: INDF <- W

However, during the GCSE phase, I get this:

2618: W <- pseudo-59
2619: clobber INDF
2620: FSR <- pseudo-59  ;; Not allowed -- not moved through W !!!
2621: use FSR
2622: W <- TMP
2623: INDF <- W

Again, it just seems that somewhere I'm not instructing gcc properly
that moves may only involve the W register. I've defined expanders for
addqi3 and movqi so that they only emit W-move instructions, and I've
defined PREFERRED_RELOAD_CLASS and SECONDARY_RELOAD_CLASS to involve
the W register in all reloads. I've also defined expanders for
reload_outqi and reload_inqi which only use W-moves.

So what's left?

Thanks for your help, I'm learning plenty! I'm attaching the current
state of the port, in case anyone wants to see it so far...

--Rob

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