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Hi all,
First, thanks for all the help I've been getting. I appreciate it very much.
Here's my problem. On my processor, moves may only take place through
the W register (the accumulator). Thus, the only valid moves are:
(memory | register | immediate) -> W
W -> (memory | register)
So if I want to move one register to another, it has to go through the
W register.
I've defined a class for the W register (W_REG), and a class for
general registers, which are all the registers except the W register.
I then defined the constraint letter 'w' to stand for the W_REG class.
Finally, I have these insns in my machine description:
(define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=w,r,m")
(match_operand:QI 1 "general_operand" "g,w,w"))]
""
"\tmovf %1,%0"
[(set_attr "cc" "z")]
)
(define_insn "addqi3"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(plus:QI (match_operand:QI 1 "register_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "r,i")))]
""
"\taddf %1,%0"
[(set_attr "cc" "all")]
)
The problem is that gcc is generating register moves that don't go
through the W register, such as:
(insn 815 86 88 0 ../../Desktop/gcc-3.4.3/gcc/libgcc2.c:462 (set (reg:QI 8 R57)
(reg/f:QI 49 R20/FP)) 0 {movqi} (nil)
(nil))
and that causes gcc to bomb out saying that the insn doesn't satisfy
its constraints (obviously because the move doesn't involve W).
How do I prevent gcc from generating such instructions? Or do I have
to write a machine description that accepts R1->R2 moves, but define a
temporary register X and then write assembler output for (W->X, R1->W,
W->R2, X->W)?
I'm including my current port, in case anyone needs to look at it for
further info.
Thanks for any help...
BTW, in case anyone has seen my previous posts and is wondering, I'm
trying to write the port by first being very permissive in what the
processor will accept, and then slowly increasing the constraints
(thus increasing the problems) until I match the processor's specs.
--Rob
(slowly working on a port for a VERY limited processor)
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