Request for documentation: Do "define_instruction_and_split" patterns apply also in the combiner pass?

[Björn Haase <bjoern dot m dot haase at web dot de>]

Hi,

I am presently working on the back-end of the avr port and got stuck when
planning improvements of the back-end. When looking at the arm port, e.g.,
it seems that the compiler knows "define_instruction_and_split" patterns
that are so far not documented in the gcc manual. According to the name, it
seems that this is exactly what I am presently looking for: Splitting  DI,SI
and HI operations to a sequence of the QI instructions that the avr target
natively knows. Unlike the examples that I have seen in the arm machine
description, I would like, however, to make the compiler use this pattern in
the combine pass already. I have the hope, that this way, one could give the
register allocator more flexibility and minimize the amount of registers
used. Therefore my question:

- Does the compiler try to match "define_instruction_and_split" patterns
also during the combine phase?
- Is there any more detailed description on how to use this type of pattern
?
- If there is no documentation, which source file should I look at more
closely?

Thanks,

Björn