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Re: SPE scalar float instructions
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: Zack Weinberg <zack at codesourcery dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 15 Dec 2004 12:59:55 -0400
- Subject: Re: SPE scalar float instructions
- References: <87wtvkb52c.fsf@codesourcery.com>
On Tue, Dec 14, 2004 at 07:42:19PM -0800, Zack Weinberg wrote:
>
> Currently, the SPE scalar float instructions are predicated on
> TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for DFmode)
> but not on TARGET_SPE. This can cause problems in an embedded context
> - as one of CodeSourcery's customers points out,
>
> > This will indeed post a problem, because those instructions require
> > MSR[SPE] bit be set, which is not true for all cases. SPE unavailable
> > exception may result.
I'm not sure I follow the above? (??)
>
> I'm wondering if TARGET_SPE should be added to the controlling
> condition for all those instructions. Thoughts?
As Kumar mentioned, a there may be a chip with SPE but not FP in the
GPRs.
Also, suppose you have -mspe=yes -mfloat-gprs=no (or the opposite).
Aldy