--- ../gcc_cvs/gcc/gcc/config/m68k/m68k.md	2004-01-31 11:48:27.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k.md	2004-10-26 11:32:22.000000000 +0530
@@ -114,8 +114,13 @@
 ;; UNSPEC usage:
 
 (define_constants
-  [(UNSPEC_SIN  1)
-   (UNSPEC_COS  2)
+  [(UNSPEC_SIN     1)
+   (UNSPEC_COS     2)
+   (UNSPEC_PIC     3)
+   (UNSPEC_GOT     4)
+   (UNSPEC_GOTOFF  5)
+   (UNSPEC_PLT     6)
+   (UNSPEC_GOTPLT  7)
   ])
 
 ;; UNSPEC_VOLATILE usage:
@@ -237,7 +242,7 @@
 (define_expand "tstsf"
   [(set (cc0)
 	(match_operand:SF 0 "general_operand" ""))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "
 {
   m68k_last_compare_had_fp_operands = 1;
@@ -246,18 +251,29 @@
 (define_insn ""
   [(set (cc0)
 	(match_operand:SF 0 "general_operand" "fdm"))]
-  "TARGET_68881"
-{
+  "TARGET_68881 && !TARGET_CFV4E"
+ {
   cc_status.flags = CC_IN_68881;
   if (FP_REG_P (operands[0]))
     return "ftst%.x %0";
   return "ftst%.s %0";
 })
 
+(define_insn "tstsf_v4e"
+  [(set (cc0)
+        (match_operand:SF 0 "general_operand" "fd<Q>U"))]
+  "TARGET_CFV4E"
+{
+  cc_status.flags = CC_IN_68881;
+  if (FP_REG_P (operands[0]))
+    return "ftst%.d %0";
+  return "ftst%.s %0";
+})
+
 (define_expand "tstdf"
   [(set (cc0)
 	(match_operand:DF 0 "general_operand" ""))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "
 {
   m68k_last_compare_had_fp_operands = 1;
@@ -266,14 +282,23 @@
 (define_insn ""
   [(set (cc0)
 	(match_operand:DF 0 "general_operand" "fm"))]
-  "TARGET_68881"
+  "TARGET_68881 && !TARGET_CFV4E"
 {
   cc_status.flags = CC_IN_68881;
   if (FP_REG_P (operands[0]))
     return "ftst%.x %0";
   return "ftst%.d %0";
 })
-
+(define_insn "tstdf_v4e"
+  [(set (cc0)
+        (match_operand:DF 0 "general_operand" "f<Q>U"))]
+  "TARGET_CFV4E"
+{
+  cc_status.flags = CC_IN_68881;
+  return "ftst%.d %0";
+})
+
+
 ;; compare instructions.
 
 (define_expand "cmpdi"
@@ -364,8 +389,8 @@
 
 (define_insn ""
   [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
-		 (match_operand:SI 1 "general_operand" "r,mrKs")))]
+	(compare (match_operand:SI 0 "nonimmediate_operand" "mrKi,r")
+		 (match_operand:SI 1 "general_operand" "r,mrKi")))]
   "TARGET_COLDFIRE"
 {
   if (REG_P (operands[1])
@@ -458,10 +483,12 @@
   [(set (cc0)
 	(compare (match_operand:DF 0 "general_operand" "")
 		 (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "
 {
   m68k_last_compare_had_fp_operands = 1;
+  if ( TARGET_CFV4E && (!reload_completed) )
+    operands[1] = force_reg(DFmode, operands[1]);
 }")
 
 (define_insn ""
@@ -494,14 +521,47 @@
 #endif
 })
 
+
+(define_insn "cmpdf_v4e"
+  [(set (cc0)
+        (compare (match_operand:DF 0 "general_operand" "f,<Q>U")
+                 (match_operand:DF 1 "fpu_operand" "f<Q>U,f")))]
+  "TARGET_CFV4E"
+{
+  cc_status.flags = CC_IN_68881;
+#ifdef SGS_CMP_ORDER
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+        return "fcmp%.d %0,%1";
+      else
+        return "fcmp%.d %0,%1";
+    }
+  cc_status.flags |= CC_REVERSED;
+  return "fcmp%.d %1,%0";
+#else
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+        return "fcmp%.d %1,%0";
+      else
+        return "fcmp%.d %1,%0";
+    }
+  cc_status.flags |= CC_REVERSED;
+  return "fcmp%.d %0,%1";
+#endif
+})
+
 (define_expand "cmpsf"
  [(set (cc0)
        (compare (match_operand:SF 0 "general_operand" "")
 		(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881||TARGET_CFV4E"
  "
 {
   m68k_last_compare_had_fp_operands = 1;
+  if ( TARGET_CFV4E && (!reload_completed) )
+    operands[1] = force_reg(SFmode, operands[1]);
 }")
 
 (define_insn ""
@@ -533,7 +593,37 @@
   return "fcmp%.s %f0,%1";
 #endif
 })
-
+
+(define_insn "cmpsf_v4e"
+  [(set (cc0)
+        (compare (match_operand:SF 0 "general_operand" "f,<Q>U")
+                 (match_operand:SF 1 "fpu_operand" "f<Q>U,f")))]
+  "TARGET_CFV4E"
+{
+  cc_status.flags = CC_IN_68881;
+#ifdef SGS_CMP_ORDER
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+        return "fcmp%.d %0,%1";
+      else
+        return "fcmp%.s %0,%f1";
+    }
+  cc_status.flags |= CC_REVERSED;
+  return "fcmp%.s %1,%f0";
+#else
+  if (FP_REG_P (operands[0]))
+    {
+      if (FP_REG_P (operands[1]))
+        return "fcmp%.d %1,%0";
+      else
+        return "fcmp%.s %f1,%0";
+    }
+  cc_status.flags |= CC_REVERSED;
+  return "fcmp%.s %f0,%1";
+#endif
+})
+
 ;; Recognizers for btst instructions.
 
 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
@@ -721,13 +811,24 @@
   ""
   "
 {
-  if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
+
+  if ( flag_pic && !TARGET_PCREL && TARGET_CFV4E )
+    {
+       m68k_expand_move (SImode, operands); DONE;
+
+       //rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+       //operands[1] = legitimize_pic_address (operands[1], SImode, temp);
+       //emit_insn( gen_movsi_cfv4e_got(operands[0], operands[1], temp));
+       //DONE;
+    } 
+  else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
     {
       /* The source is an address which requires PIC relocation.
          Call legitimize_pic_address with the source, mode, and a relocation
          register (a new pseudo, or the final destination if reload_in_progress
          is set).   Then fall through normally */
       rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+      
       operands[1] = legitimize_pic_address (operands[1], SImode, temp);
     }
   else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
@@ -761,7 +862,19 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
 	(match_operand:SI 1 "general_operand" "g,r<Q>"))]
   "TARGET_COLDFIRE"
-  "* return output_move_simode (operands);")
+{
+     return output_move_simode (operands);
+})
+
+
+(define_insn "movsi_cfv4e_got"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
+        (match_operand:SI 1 "general_src_operand" "g"))]
+  "flag_pic && TARGET_CFV4E"
+{
+     return output_move_simode (operands);
+})
+
 
 ;; Special case of fullword move, where we need to get a non-GOT PIC
 ;; reference into an address register.
@@ -770,9 +883,9 @@
         (match_operand:SI 1 "pcrel_address" ""))]
   "TARGET_PCREL"
 {
-  if (push_operand (operands[0], SImode))
-    return "pea %a1";
-  return "lea %a1,%0";
+    if (push_operand (operands[0], SImode))
+      return "pea %a1";
+    return "lea %a1,%0";
 })
 
 (define_expand "movhi"
@@ -854,6 +967,36 @@
   "!TARGET_COLDFIRE"
   "")
 
+(define_expand "reload_insf"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (match_operand:SF 1 "general_operand" "mf"))
+   (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+  "TARGET_CFV4E"
+  "
+{
+  if (emit_move_sequence (operands, SFmode, operands[2]))
+    DONE;
+
+  /* We don't want the clobber emitted, so handle this ourselves. */
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+  DONE;
+}")
+
+(define_expand "reload_outsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+        (match_operand:SF 1 "register_operand" "f"))
+   (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+  "TARGET_CFV4E"
+  "
+{
+  if (emit_move_sequence (operands, SFmode, operands[2]))
+    DONE;
+
+  /* We don't want the clobber emitted, so handle this ourselves. */
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+  DONE;
+}")
+
 (define_expand "movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
@@ -912,19 +1055,192 @@
   return "move%.l %1,%0";
 })
 
-(define_insn ""
+;(define_insn ""
+;  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
+;	(match_operand:SF 1 "general_operand" "g,r"))]
+;  "TARGET_COLDFIRE"
+;{
+;  return "move%.l %1,%0";
+;})
+
+(define_insn "movsf_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f,    f,mr,f,r<Q>,f,m")
+        (match_operand:SF 1 "general_operand"      " f,     r<Q>U,f,rm,F,F,   m,f"))]
+  "TARGET_CFV4E"
+{
+  if (which_alternative == 4 || which_alternative == 5) {
+    rtx xoperands[2];
+    REAL_VALUE_TYPE r;
+    long l;
+    REAL_VALUE_FROM_CONST_DOUBLE(r, operands[1]);
+    REAL_VALUE_TO_TARGET_SINGLE(r, l);
+    xoperands[0] = operands[0];
+    xoperands[1] = GEN_INT(l);
+    if (which_alternative == 5) {
+      if (l == 0) {
+        if (ADDRESS_REG_P (xoperands[0]))
+          output_asm_insn("sub%.l %0,%0", xoperands);
+        else
+          output_asm_insn("clr%.l %0", xoperands);
+      } else
+        if (GET_CODE (operands[0]) == MEM
+            && symbolic_operand (XEXP (operands[0], 0), SImode))
+          output_asm_insn("move%.l %1,%-;move%.l %+,%0", xoperands);
+        else
+          output_asm_insn("move%.l %1,%0", xoperands);
+      return "\";
+    }
+    if (l != 0)
+      output_asm_insn("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
+    else
+      output_asm_insn("clr%.l %-;fsmove%.s %+,%0", xoperands);
+    return "\";
+  }
+  if (FP_REG_P (operands[0]))
+    {
+      if (ADDRESS_REG_P (operands[1]))
+        return "move%.l %1,%-;f%$smove%.s %+,%0";
+      if (FP_REG_P (operands[1]))
+        return "f%$move%.d %1,%0";
+      if (GET_CODE (operands[1]) == CONST_DOUBLE)
+        return output_move_const_single (operands);
+      return "f%$move%.s %f1,%0";
+    }
+  if (FP_REG_P (operands[1]))
+    {
+      if (ADDRESS_REG_P (operands[0]))
+        return "fmove%.s %1,%-;move%.l %+,%0";
+      return "fmove%.s %f1,%0";
+    }
+  if (operands[1] == CONST0_RTX (SFmode)
+      /* clr insns on 68000 read before writing.
+         This isn't so on the 68010, but we have no TARGET_68010.  */
+      && ((TARGET_68020 || TARGET_COLDFIRE)
+          || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+    {
+      if (ADDRESS_REG_P (operands[0]))
+        {
+          /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
+          if (!TARGET_68040 && !TARGET_68060)
+            return "sub%.l %0,%0";
+          else
+            {
+#ifdef MOTOROLA
+#ifdef SGS
+              /* Many SGS assemblers croak on size specifiers for constants. */
+              return "lea 0,%0";
+#else
+              return "lea 0.w,%0";
+#endif
+#else
+              return "lea 0:w,%0";
+#endif
+            }
+        }
+      /* moveq is faster on the 68000.  */
+      if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
+        {
+#if defined(MOTOROLA) && !defined(CRDS)
+          return "moveq%.l %#0,%0";
+#else
+          return "moveq %#0,%0";
+#endif
+        }
+      return "clr%.l %0";
+    }
+  return "move%.l %1,%0";
+})
+
+(define_insn "movsf_cf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
-	(match_operand:SF 1 "general_operand" "g,r"))]
-  "TARGET_COLDFIRE"
+        (match_operand:SF 1 "general_operand" "g,r"))]
+  "TARGET_COLDFIRE && !TARGET_CFV4E"
 {
-  return "move%.l %1,%0";
+ return "move%.l %1,%0";})
+
+(define_expand "reload_indf"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (match_operand:DF 1 "general_operand" "mf"))
+   (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+  "TARGET_CFV4E"
+  {
+    if (emit_move_sequence (operands, DFmode, operands[2]))
+      DONE;
+
+  /* We don't want the clobber emitted, so handle this ourselves. */
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+  DONE;
 })
 
+(define_expand "reload_outdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+        (match_operand:DF 1 "register_operand" "f"))
+   (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+  "TARGET_CFV4E"
+{
+  if (emit_move_sequence (operands, DFmode, operands[2]))
+    DONE;
+
+  /* We don't want the clobber emitted, so handle this ourselves. */
+  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+  DONE;
+})
+
+(define_insn ""
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g,f")
+	(match_operand:SF 1 "general_operand" "g,r,f"))]
+  "TARGET_COLDFIRE"
+{
+  return \"move%.l %1,%0\";})
+
 (define_expand "movdf"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
-  "")
+{
+  if (TARGET_CFV4E) 
+    if (emit_move_sequence (operands, DFmode, 0))
+      DONE;
+})
+
+;  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,    <Q>U,r,f,r")
+;        (match_operand:DF 1 "general_operand"      " f<Q>U,f,   f,r,r"))]
+
+(define_insn "movdf_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,    <Q>U,r,f,r,f,m,f")
+        (match_operand:DF 1 "general_operand"      " f<Q>U,f,   f,r,r,m,f,E"))]
+  "TARGET_CFV4E"
+{
+  if (which_alternative == 4)
+    return "move%.l %1,%0;move%.l %R1,%R0"; 
+  if (which_alternative == 2)
+    return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
+  if (which_alternative == 3)
+    return "move%.l %R1,%-;move%.l %1,%-;f%&move%.d %+,%0";
+  if (which_alternative == 7) {
+    rtx xoperands[3];
+    REAL_VALUE_TYPE r;
+    long l[2];
+    REAL_VALUE_FROM_CONST_DOUBLE(r, operands[1]);
+    REAL_VALUE_TO_TARGET_DOUBLE(r, l);
+    xoperands[0] = operands[0];
+    xoperands[1] = GEN_INT(l[0]);
+    xoperands[2] = GEN_INT(l[1]);
+    if (operands[1] == CONST0_RTX (DFmode))
+      output_asm_insn("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
+                      xoperands);
+    else
+      if (l[1] == 0)
+        output_asm_insn("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
+                        xoperands);
+      else
+        output_asm_insn("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
+                        xoperands);
+    return "\";
+  }
+  return "fmove%.d %1,%0";
+})
+
 
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
@@ -1542,16 +1858,37 @@
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
   "TARGET_68020 || TARGET_COLDFIRE"
   "extb%.l %0")
-
+
 ;; Conversions between float and double.
 
 (define_expand "extendsfdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(float_extend:DF
 	 (match_operand:SF 1 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "extendsfdf2_v4e"
+  [(set (match_operand:DF 0 "general_operand" "=f,f")
+        (float_extend:DF
+         (match_operand:SF 1 "general_operand" "f,<Q>U")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
+    {
+      if (REGNO (operands[0]) == REGNO (operands[1]))
+        {
+          /* Extending float to double in an fp-reg is a no-op.
+             NOTICE_UPDATE_CC has already assumed that the
+             cc will be set.  So cancel what it did.  */
+          cc_status = cc_prev_status;
+          return "\";
+        }
+      return "f%&move%.d %1,%0";
+    }
+  return "f%&move%.s %f1,%0";
+})
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
 	(float_extend:DF
@@ -1570,8 +1907,6 @@
 	}
       return "f%&move%.x %1,%0";
     }
-  if (FP_REG_P (operands[0]))
-    return "f%&move%.s %f1,%0";
   if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
     {
       output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
@@ -1587,9 +1922,18 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(float_truncate:SF
 	  (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "truncdfsf2_v4e"
+  [(set (match_operand:SF 0 "general_operand" "=f,d<Q>U")
+        (float_truncate:SF
+          (match_operand:DF 1 "general_operand" "<Q>U,f")))]
+  "TARGET_CFV4E"
+  "@
+  f%$move%.d %1,%0
+  fmove%.s %1,%0")
+
 ;; On the '040 we can truncate in a register accurately and easily.
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -1620,9 +1964,16 @@
 (define_expand "floatsisf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(float:SF (match_operand:SI 1 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "floatsisf2_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (float:SF (match_operand:SI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "f%$move%.l %1,%0")
+
+
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(float:SF (match_operand:SI 1 "general_operand" "dmi")))]
@@ -1632,36 +1983,90 @@
 (define_expand "floatsidf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(float:DF (match_operand:SI 1 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "floatsidf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (float:DF (match_operand:SI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "f%&move.l %1,%0")
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(float:DF (match_operand:SI 1 "general_operand" "dmi")))]
   "TARGET_68881"
   "f%&move%.l %1,%0")
 
-(define_insn "floathisf2"
+(define_expand "floathisf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(float:SF (match_operand:HI 1 "general_operand" "dmn")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "floathisf2_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (float:SF (match_operand:HI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "fsmove%.w %1,%0")
+
+(define_insn "floathisf2_68881"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
   "TARGET_68881"
   "f%$move%.w %1,%0")
 
-(define_insn "floathidf2"
+(define_expand "floathidf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(float:DF (match_operand:HI 1 "general_operand" "dmn")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "floathidf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (float:DF (match_operand:HI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "fmove%.w %1,%0")
+
+(define_insn "floathidf2_68881"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
   "TARGET_68881"
   "fmove%.w %1,%0")
 
-(define_insn "floatqisf2"
+(define_expand "floatqisf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(float:SF (match_operand:QI 1 "general_operand" "dmn")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "floatqisf2_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (float:SF (match_operand:QI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "fsmove%.b %1,%0")
+
+(define_insn "floatqisf2_68881"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
   "TARGET_68881"
   "fmove%.b %1,%0")
 
-(define_insn "floatqidf2"
+(define_expand "floatqidf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(float:DF (match_operand:QI 1 "general_operand" "dmn")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "floatqidf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (float:DF (match_operand:QI 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "fmove%.b %1,%0")
+
+(define_insn "floatqidf2_68881"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
   "TARGET_68881"
   "f%&move%.b %1,%0")
 
@@ -1706,9 +2111,23 @@
 ;; Convert a float to a float whose value is an integer.
 ;; This is the first stage of converting it to an integer type.
 
-(define_insn "ftruncdf2"
+(define_expand "ftruncdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
+  "(TARGET_68881 && !TARGET_68040) || TARGET_CFV4E"
+  "")
+
+(define_insn "ftruncdf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (fix:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+{
+  return "fintrz%.d %1,%0";
+})
+
+(define_insn "ftruncdf2_68881"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
   "TARGET_68881 && !TARGET_68040"
 {
   if (FP_REG_P (operands[1]))
@@ -1716,9 +2135,25 @@
   return "fintrz%.d %f1,%0";
 })
 
-(define_insn "ftruncsf2"
+(define_expand "ftruncsf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
+  "(TARGET_68881 && !TARGET_68040) || TARGET_CFV4E"
+  "")
+
+(define_insn "ftruncsf2_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (fix:SF (match_operand:SF 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[1]))
+    return "fintrz%.d %1,%0";
+  return "fintrz%.s %1,%0";
+})
+
+(define_insn "ftruncsf2_68881"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
   "TARGET_68881 && !TARGET_68040"
 {
   if (FP_REG_P (operands[1]))
@@ -1728,42 +2163,114 @@
 
 ;; Convert a float whose value is an integer
 ;; to an actual integer.  Second stage of converting float to integer type.
-(define_insn "fixsfqi2"
+(define_expand "fixsfqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(fix:QI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "fixsfqi2_v4e"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:QI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.b %1,%0")
+
+(define_insn "fixsfqi2_68881"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
+        (fix:QI (match_operand:SF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.b %1,%0")
 
-(define_insn "fixsfhi2"
+(define_expand "fixsfhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(fix:HI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_68881|| TARGET_CFV4E"
+  "")
+
+(define_insn "fixsfhi2_v4e"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:HI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.w %1,%0")
+
+(define_insn "fixsfhi2_68881"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
+        (fix:HI (match_operand:SF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.w %1,%0")
 
-(define_insn "fixsfsi2"
+(define_expand "fixsfsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
 	(fix:SI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "fixsfsi2_v4e"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:SI (match_operand:SF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.l %1,%0")
+
+(define_insn "fixsfsi2_68881"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
+        (fix:SI (match_operand:SF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.l %1,%0")
 
-(define_insn "fixdfqi2"
+(define_expand "fixdfqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(fix:QI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "fixdfqi2_v4e"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:QI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.b %1,%0")
+
+(define_insn "fixdfqi2_68881"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
+        (fix:QI (match_operand:DF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.b %1,%0")
 
-(define_insn "fixdfhi2"
+(define_expand "fixdfhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(fix:HI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "fixdfhi2_v4e"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:HI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.w %1,%0")
+
+(define_insn "fixdfhi2_68881"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
+        (fix:HI (match_operand:DF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.w %1,%0")
 
-(define_insn "fixdfsi2"
+(define_expand "fixdfsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
 	(fix:SI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "fixdfsi2_v4e"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
+        (fix:SI (match_operand:DF 1 "general_operand" "f")))]
+  "TARGET_CFV4E"
+  "fmove%.l %1,%0")
+
+(define_insn "fixdfsi2_68881"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
+        (fix:SI (match_operand:DF 1 "general_operand" "f")))]
   "TARGET_68881"
   "fmove%.l %1,%0")
-
+
 ;; add instructions
 
 (define_insn "adddi_lshrdi_63"
@@ -2219,9 +2726,17 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(plus:DF (match_operand:DF 1 "general_operand" "")
 		 (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "adddf3_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (plus:DF (match_operand:DF 1 "general_operand" "%0")
+                 (match_operand:DF 2 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+  "fadd%.d %2,%0")
+
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
@@ -2258,8 +2773,20 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(plus:SF (match_operand:SF 1 "general_operand" "")
 		 (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881"
-  "")
+  "(TARGET_68881 || TARGET_CFV4E)"
+  "
+  ")
+
+(define_insn "addsf3_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (plus:SF (match_operand:SF 1 "general_operand" "%0")
+                 (match_operand:SF 2 "general_operand" "fd<Q>U")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[2]))
+    return "f%$add%.d %2,%0";
+  return "fadd%.s %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -2457,9 +2984,16 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(minus:DF (match_operand:DF 1 "general_operand" "")
 		  (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "subdf3_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (minus:DF (match_operand:DF 1 "general_operand" "0")
+                  (match_operand:DF 2 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+  "fsub%.d %2,%0")
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(minus:DF (match_operand:DF 1 "general_operand" "0")
@@ -2496,9 +3030,21 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(minus:SF (match_operand:SF 1 "general_operand" "")
 		  (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "subsf3_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (minus:SF (match_operand:SF 1 "general_operand" "0")
+                  (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+  "TARGET_CFV4E"
+{
+  if (!FP_REG_P (operands[2]))
+    return "fsub%.s %2,%0";
+  return "fssub%.d %2,%0";
+})
+
+
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(minus:SF (match_operand:SF 1 "general_operand" "0")
@@ -2778,9 +3324,16 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(mult:DF (match_operand:DF 1 "general_operand" "")
 		 (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "muldf3_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (mult:DF (match_operand:DF 1 "general_operand" "%0")
+                 (match_operand:DF 2 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+  "fmul%.d %2,%0")
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
@@ -2824,8 +3377,18 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(mult:SF (match_operand:SF 1 "general_operand" "")
 		 (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
+(define_insn "mulsf3_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (mult:SF (match_operand:SF 1 "general_operand" "%0")
+                 (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+  "TARGET_CFV4E"
+{
+  if (!FP_REG_P (operands[2]))
+    return "fmul%.s %2,%0";
+  return "fsmul%.d %2,%0";
+})
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -2881,9 +3444,16 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(div:DF (match_operand:DF 1 "general_operand" "")
 		(match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "divdf3_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (div:DF (match_operand:DF 1 "general_operand" "0")
+                (match_operand:DF 2 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+  "fdiv%.d %2,%0")
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(div:DF (match_operand:DF 1 "general_operand" "0")
@@ -2920,9 +3490,20 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(div:SF (match_operand:SF 1 "general_operand" "")
 		(match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881"
+  "TARGET_68881 || TARGET_CFV4E"
   "")
 
+(define_insn "divsf3_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (div:SF (match_operand:SF 1 "general_operand" "0")
+                (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[2]))
+    return "fsdiv%.d %2,%0";
+  return "fdiv%.s %2,%0";
+})
+
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(div:SF (match_operand:SF 1 "general_operand" "0")
@@ -3669,9 +4250,8 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(neg:SF (match_operand:SF 1 "general_operand" "")))]
   ""
-  "
 {
-  if (!TARGET_68881)
+  if (!TARGET_68881 && !TARGET_CFV4E)
     {
       rtx result;
       rtx target;
@@ -3690,7 +4270,14 @@
       emit_move_insn (operands[0], operands[0]);
       DONE;
     }
-}")
+})
+
+                                                                                                                            
+(define_insn "negsf2_v4e"
+  [(set (match_operand:SF 0 "general_operand" "=f")
+        (neg:SF (match_operand:SF 1 "general_operand" "d<Q>U")))]
+  "TARGET_CFV4E"
+  "f%$neg%.s %1,%0")
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
@@ -3707,13 +4294,28 @@
   return "f%$neg%.s %f1,%0";
 })
 
+(define_insn ""
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
+        (neg:SF (match_operand:SF 1 "general_operand" "fd<Q>U,0")))]
+  "TARGET_CFV4E"
+{
+  if (DATA_REG_P (operands[0]))
+    {
+      operands[1] = GEN_INT (31);
+      return "bchg %1,%0";
+    }
+  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
+    return "fsneg%.d %1,%0";
+  return "fsneg%.s %1,%0";
+})
+
 (define_expand "negdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(neg:DF (match_operand:DF 1 "general_operand" "")))]
   ""
   "
 {
-  if (!TARGET_68881)
+  if (!TARGET_68881 && !TARGET_CFV4E)
     {
       rtx result;
       rtx target;
@@ -3741,6 +4343,12 @@
     }
 }")
 
+(define_insn "negdf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (neg:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+  "fneg%.d %1,%0")
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
 	(neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
@@ -3752,15 +4360,47 @@
       return "bchg %1,%0";
     }
   if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return "f%&neg%.x %1,%0";
-  return "f%&neg%.d %f1,%0";
+    return \"f%&neg%.x %1,%0\";
+  return \"f%&neg%.d %f1,%0\";
 })
-
+
+(define_insn ""
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
+        (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
+  "TARGET_CFV4E"
+{
+  if (DATA_REG_P (operands[0]))
+    {
+      operands[1] = GEN_INT (31);
+      return "bchg %1,%0";
+    }
+  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
+    return "fdneg%.d %1,%0";
+  return "fdneg%.d %1,%0";
+})
+
 ;; Sqrt instruction for the 68881
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "sqrtsf2_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (sqrt:SF (match_operand:SF 1 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[1]))
+    return "fssqrt%.d %1,%0";
+  else
+    return "fssqrt%.s %1,%0";
+})
+
+(define_insn "sqrtsf2_68881"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
   "TARGET_68881"
 {
   if (FP_REG_P (operands[1]))
@@ -3772,6 +4412,20 @@
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
+  "TARGET_68881 || TARGET_CFV4E"
+  "")
+
+(define_insn "sqrtdf2_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (sqrt:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+{
+  return "fdsqrt%.d %1,%0";
+})
+
+(define_insn "sqrtdf2_68881"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
   "TARGET_68881"
 {
   if (FP_REG_P (operands[1]))
@@ -3789,7 +4443,7 @@
   ""
   "
 {
-  if (!TARGET_68881)
+  if (!TARGET_68881 || !TARGET_CFV4E)
     {
       rtx result;
       rtx target;
@@ -3810,6 +4464,16 @@
     }
 }")
 
+(define_insn "abssf_v4e"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+        (abs:SF (match_operand:SF 1 "general_operand" "fd<Q>U")))]
+  "TARGET_CFV4E"
+{
+  if (FP_REG_P (operands[1]))
+    return "fsabs.d %1,%0";
+  return "fsabs%.s %1,%0";
+})
+
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
 	(abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
@@ -3826,7 +4490,7 @@
   ""
   "
 {
-  if (!TARGET_68881)
+  if (!TARGET_68881 || TARGET_CFV4E)
     {
       rtx result;
       rtx target;
@@ -3854,6 +4518,14 @@
     }
 }")
 
+(define_insn "absdf_v4e"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+        (abs:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+  "TARGET_CFV4E"
+{
+  return "fdabs%.d %1,%0";
+})
+
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
 	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
@@ -5087,7 +5759,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ((TARGET_68060 || TARGET_CFV4E ) && m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -5109,7 +5781,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ( (TARGET_68060 || TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -5131,7 +5803,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ((TARGET_68060||TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -5168,7 +5840,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ((TARGET_68060||TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -5205,7 +5877,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ((TARGET_68060 || TARGET_CFV4E)&& m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -5242,7 +5914,7 @@
   ""
   "
 {
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+  if ((TARGET_68060|| TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
     {
       m68k_last_compare_had_fp_operands = 0;
       FAIL;
@@ -6408,6 +7080,18 @@
   ""
   "
 {
+rtx insn;
+  if (flag_pic && TARGET_CFV4E)
+    {
+       if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+          && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+          current_function_uses_pic_offset_table = 1;
+
+       //if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
+          XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 
+       insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
+       DONE; 
+    }
   if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
     SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
 }")
@@ -6439,6 +7123,24 @@
   return "";
 })
 
+
+/* Added for handling of PIC in cfv4e   */
+(define_expand "call_exp"
+  [(call (match_operand:QI 0 "constant_call_address_operand" "")
+         (match_operand 1 "" ""))]
+  "flag_pic && TARGET_CFV4E"
+  "")
+
+/* Added for handling of PIC in cfv4e  */
+(define_insn "*call_0"
+  [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
+         (match_operand 1 "" ""))]
+  "flag_pic && TARGET_CFV4E"
+  "*
+{
+   return \"jsr %a1@GOT(%%a5)\";
+}")
+
 ;; Call subroutine, returning value in operand 0
 ;; (which must be a hard register).
 ;; See comments before "call" regarding PIC calls.
@@ -6450,7 +7152,19 @@
   ""
   "
 {
-  if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+rtx insn;
+  if ( flag_pic && TARGET_CFV4E )
+    {
+      if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+           && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
+                current_function_uses_pic_offset_table = 1;
+      //if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
+         XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
+      insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
+                                             operands[2]));
+      DONE;
+    }
+  else if ( flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
     SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
 }")
 
@@ -6475,12 +7189,34 @@
 	(call (match_operand:QI 1 "memory_operand" "o")
 	      (match_operand:SI 2 "general_operand" "g")))]
   ;; Operand 2 not really used on the m68000.
-  "flag_pic"
+  "flag_pic "
 {
   m68k_output_pic_call(operands[1]);
   return "";
 })
 
+/* Added for handling of PIC in cfv4e  */
+(define_expand "call_value_exp"
+  [(set (match_operand 0 "" "")
+        (call (match_operand:QI 1 "" "")
+              (match_operand:SI 2 "" "")))]
+  "flag_pic && TARGET_CFV4E"
+  "")
+
+/* Added for handling of PIC in cfv4e  */
+(define_insn "*call_value_0"
+  [(set (match_operand 0 "" "")
+        (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
+              (match_operand:SI 2 "" "")))]
+  "flag_pic && TARGET_CFV4E"
+  "*
+{
+   return \"jsr %a1@GOT(%%a5)\";
+}")
+
+
+
+
 ;; Call subroutine returning any type.
 
 (define_expand "untyped_call"
@@ -6839,6 +7575,8 @@
   return "";
 })
 
+
+
 
 (define_expand "tstxf"
   [(set (cc0)
@@ -6849,7 +7587,7 @@
 (define_insn ""
   [(set (cc0)
 	(match_operand:XF 0 "nonimmediate_operand" "fm"))]
-  "TARGET_68881"
+  "TARGET_68881 && !TARGET_CFV4E"
 {
   cc_status.flags = CC_IN_68881;
   return "ftst%.x %0";