This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: warning: right shift count >= width of type


> > but it's surely only an issue of bugward-compatibility:
> > mathematically, there's really no problem with right-shifting more
> > than the width of the integer, all that happens is that _all_ the
> > bits drop out the right-hand side and you're left with nothing.
>
>That's not what all hardware actually does with shift instructions.
>
> > ISTM reasonable that the result of a right-shift by 32 bits could
> > be assumed to be the same thing you get if you right-shift by 1 bit
> > 32 times....
>
>The chip designers don't agree.

They *definitely* don't agree.  Most shift hardware is designed as a
barrel shifter which is a large combinational logic block that takes the
n-bits of the shift count and using them determine what each bit of
the result is supposed to be.  This allows a shift that takes only one
clock, wheter the shift is arithmetic or logical, right or left, and a
shift count from 0 up to the number of bits in the register-1.

Any shift count outside of that range is considered "undefined".

n 1-bit shifts is equivient to 1 n-bit shift only if n is less than
the size of the register in bits, at least for a hardware
implementation described above.

-- 
Peter Barada
peter@the-baradas.com


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]