This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: RFC: PR14880 vec_duplicate or vec_select?
- From: Dorit Naishlos <DORIT at il dot ibm dot com>
- To: Aldy Hernandez <aldyh at redhat dot com>
- Cc: David Edelsohn <dje at watson dot ibm dot com>, gcc at gcc dot gnu dot org
- Date: Mon, 15 Nov 2004 17:39:47 +0200
- Subject: Re: RFC: PR14880 vec_duplicate or vec_select?
> Try this.
This one works (i.e - bootstrapped and passed the vectorization testcases
on ppc-darwin).
By the way, for initialization of a vector register with an invariant (e.g.
testcase vect-25.c), we still get the following code (the invariant is in
r3):
mr r9,r3
mr r10,r3
mr r11,r3
mr r12,r3
L6:
addi r7,r1,1104
stw r9,0(r7)
stw r10,4(r7)
stw r11,8(r7)
stw r12,12(r7)
lvx v0,0,r7
stvx v0,0,r2
addi r2,r2,16
bdnz L6
instead of, say:
stw r3,0(r2)
lvewx v0,0,r2
vspltw v0,v0,0
L4:
stvx v0,r2,r0
addi r2,r2,16
bdnz L4
I'm not sure if this was part of David's concern when he opened this PR, or
should this be a separate PR.
dorit
Aldy Hernandez
<aldyh@redhat.com To: Dorit Naishlos/Haifa/IBM@IBMIL
> cc: David Edelsohn <dje@watson.ibm.com>, gcc@gcc.gnu.org
Subject: Re: RFC: PR14880 vec_duplicate or vec_select?
15/11/2004 14:39
> It bootstrapped for me on powerpc-darwin, but I get an ICE if I try to
> compile with -maltivec:
Whoops. Typo. Arghhh... I need to get my AltiVec box back.
Try this.
Thanks.
Aldy
* config/rs6000/altivec.md ("altivec_vsplth"): Rewrite with
vec_duplicate.
(altivec_vspltb): Same.
(altivec_vspltw): Same.
(altivec_vspltisb): Same.
(altivec_vspltish): Same.
(altivec_vspltisw): Same.
(altivec_vspltisw_v4sf): Same.
(define_constants): Remove UNSPEC_VSPLTISB, UNSPEC_VSPLTISW,
UNSPEC_VSPLTISH.
Move "End of vector xor's" comment to the right place.
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.24
diff -c -p -r1.24 altivec.md
*** config/rs6000/altivec.md 7 Oct 2004 16:05:34 -0000
1.24
--- config/rs6000/altivec.md 15 Nov 2004 12:37:14 -0000
***************
*** 20,29 ****
;; MA 02111-1307, USA.
(define_constants
! [(UNSPEC_VSPLTISW 141)
! (UNSPEC_VSPLTISH 140)
! (UNSPEC_VSPLTISB 139)
! (UNSPEC_VCMPBFP 50)
(UNSPEC_VCMPEQUB 51)
(UNSPEC_VCMPEQUH 52)
(UNSPEC_VCMPEQUW 53)
--- 20,26 ----
;; MA 02111-1307, USA.
(define_constants
! [(UNSPEC_VCMPBFP 50)
(UNSPEC_VCMPEQUB 51)
(UNSPEC_VCMPEQUH 52)
(UNSPEC_VCMPEQUW 53)
***************
*** 1494,1552 ****
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
136))]
"TARGET_ALTIVEC"
"vspltb %0,%1,%2"
[(set_attr "type" "vecperm")])
- ;; End of vector xor's
(define_insn "altivec_vsplth"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
137))]
"TARGET_ALTIVEC"
"vsplth %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
138))]
"TARGET_ALTIVEC"
"vspltw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISB))]
"TARGET_ALTIVEC"
"vspltisb %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltish"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISH))]
"TARGET_ALTIVEC"
"vspltish %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISW))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")]
142))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
--- 1491,1557 ----
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
[(set_attr "type" "vecsimple")])
+ ;; End of vector xor's
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (vec_duplicate:V16QI
! (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
! (parallel
! [(match_operand:QI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vspltb %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vsplth"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (vec_duplicate:V8HI
! (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
! (parallel
! [(match_operand:QI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vsplth %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (vec_duplicate:V4SI
! (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
! (parallel
! [(match_operand:QI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vspltw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (vec_duplicate:V16QI
! (match_operand:QI 1 "immediate_operand" "i")))]
"TARGET_ALTIVEC"
"vspltisb %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltish"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (vec_duplicate:V8HI
! (sign_extend:HI (match_operand:QI 1 "immediate_operand"
"i"))))]
"TARGET_ALTIVEC"
"vspltish %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (vec_duplicate:V4SI
! (sign_extend:SI (match_operand:QI 1 "immediate_operand"
"i"))))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (vec_duplicate:V4SF
! (float:SF (sign_extend:SI
! (match_operand:QI 1 "immediate_operand"
"i")))))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])