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Re: RFC: PR14880 vec_duplicate or vec_select?

> It bootstrapped for me on powerpc-darwin, but I get an ICE if I try to
> compile with -maltivec:

Whoops.  Typo.  Arghhh... I need to get my AltiVec box back.

Try this.

Thanks.
Aldy

	* config/rs6000/altivec.md ("altivec_vsplth"): Rewrite with
	vec_duplicate.
	(altivec_vspltb): Same.
	(altivec_vspltw): Same.
	(altivec_vspltisb): Same.
	(altivec_vspltish): Same.
	(altivec_vspltisw): Same.
	(altivec_vspltisw_v4sf): Same.
	(define_constants): Remove UNSPEC_VSPLTISB, UNSPEC_VSPLTISW,
	UNSPEC_VSPLTISH.
	Move "End of vector xor's" comment to the right place.

Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.24
diff -c -p -r1.24 altivec.md
*** config/rs6000/altivec.md	7 Oct 2004 16:05:34 -0000	1.24
--- config/rs6000/altivec.md	15 Nov 2004 12:37:14 -0000
***************
*** 20,29 ****
  ;; MA 02111-1307, USA.
  
  (define_constants
!   [(UNSPEC_VSPLTISW	141)
!    (UNSPEC_VSPLTISH	140)
!    (UNSPEC_VSPLTISB	139)
!    (UNSPEC_VCMPBFP       50)
     (UNSPEC_VCMPEQUB      51)
     (UNSPEC_VCMPEQUH      52)
     (UNSPEC_VCMPEQUW      53)
--- 20,26 ----
  ;; MA 02111-1307, USA.
  
  (define_constants
!   [(UNSPEC_VCMPBFP       50)
     (UNSPEC_VCMPEQUB      51)
     (UNSPEC_VCMPEQUH      52)
     (UNSPEC_VCMPEQUW      53)
***************
*** 1494,1552 ****
    "TARGET_ALTIVEC"
    "vxor %0,%1,%2"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "altivec_vspltb"
    [(set (match_operand:V16QI 0 "register_operand" "=v")
!         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
!                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
    "TARGET_ALTIVEC"
    "vspltb %0,%1,%2"
    [(set_attr "type" "vecperm")])
- ;; End of vector xor's
  
  (define_insn "altivec_vsplth"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
!         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
!                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
    "TARGET_ALTIVEC"
    "vsplth %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
!         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
!                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
    "TARGET_ALTIVEC"
    "vspltw %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisb"
    [(set (match_operand:V16QI 0 "register_operand" "=v")
!         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
! 		      UNSPEC_VSPLTISB))]
    "TARGET_ALTIVEC"
    "vspltisb %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltish"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
!         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
! 		     UNSPEC_VSPLTISH))]
    "TARGET_ALTIVEC"
    "vspltish %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
!         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
! 		     UNSPEC_VSPLTISW))]
    "TARGET_ALTIVEC"
    "vspltisw %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisw_v4sf"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
!         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
    "TARGET_ALTIVEC"
    "vspltisw %0,%1"
    [(set_attr "type" "vecperm")])
--- 1491,1557 ----
    "TARGET_ALTIVEC"
    "vxor %0,%1,%2"
    [(set_attr "type" "vecsimple")])
+ ;; End of vector xor's
  
  (define_insn "altivec_vspltb"
    [(set (match_operand:V16QI 0 "register_operand" "=v")
!         (vec_duplicate:V16QI
! 	 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
! 			(parallel
! 			 [(match_operand:QI 2 "immediate_operand" "i")]))))]
    "TARGET_ALTIVEC"
    "vspltb %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vsplth"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
! 	(vec_duplicate:V8HI
! 	 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
! 			(parallel
! 			 [(match_operand:QI 2 "immediate_operand" "i")]))))]
    "TARGET_ALTIVEC"
    "vsplth %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
! 	(vec_duplicate:V4SI
! 	 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
! 			(parallel
! 			 [(match_operand:QI 2 "immediate_operand" "i")]))))]
    "TARGET_ALTIVEC"
    "vspltw %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisb"
    [(set (match_operand:V16QI 0 "register_operand" "=v")
! 	(vec_duplicate:V16QI
! 	 (match_operand:QI 1 "immediate_operand" "i")))]
    "TARGET_ALTIVEC"
    "vspltisb %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltish"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
! 	(vec_duplicate:V8HI
! 	 (sign_extend:HI (match_operand:QI 1 "immediate_operand" "i"))))]
    "TARGET_ALTIVEC"
    "vspltish %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisw"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
! 	(vec_duplicate:V4SI
! 	 (sign_extend:SI (match_operand:QI 1 "immediate_operand" "i"))))]
    "TARGET_ALTIVEC"
    "vspltisw %0,%1"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vspltisw_v4sf"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
! 	(vec_duplicate:V4SF
! 	 (float:SF (sign_extend:SI
! 		    (match_operand:QI 1 "immediate_operand" "i")))))]
    "TARGET_ALTIVEC"
    "vspltisw %0,%1"
    [(set_attr "type" "vecperm")])
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