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Re: RFC: PR14880 vec_duplicate or vec_select?
- From: Dorit Naishlos <DORIT at il dot ibm dot com>
- To: Aldy Hernandez <aldyh at redhat dot com>
- Cc: David Edelsohn <dje at watson dot ibm dot com>, gcc at gcc dot gnu dot org
- Date: Mon, 15 Nov 2004 14:00:17 +0200
- Subject: Re: RFC: PR14880 vec_duplicate or vec_select?
> Can you give this a whirl
It bootstrapped for me on powerpc-darwin, but I get an ICE if I try to
compile with -maltivec:
gcc -O2 -maltivec vect-2.c
<built-in>:0: internal compiler error: in rs6000_common_init_builtins, at
config/rs6000/rs6000.c:8621
Breakpoint 2, rs6000_common_init_builtins () at
../../gcc/gcc/config/rs6000/rs6000.c:8621
8621 abort ();
(gdb) backtrace
#0 rs6000_common_init_builtins () at
../../gcc/gcc/config/rs6000/rs6000.c:8621
#1 0x003560ac in rs6000_common_init_builtins () at
../../gcc/gcc/config/rs6000/rs6000.c:8623
#2 0x00047ff8 in c_common_nodes_and_builtins () at
../../gcc/gcc/c-common.c:3229
#3 0x0001089c in c_init_decl_processing () at ../../gcc/gcc/c-decl.c:2564
#4 0x00058d48 in c_objc_common_init () at
../../gcc/gcc/c-objc-common.c:163
#5 0x00319804 in toplev_main (argc=6422528, argv=0x20000000) at
../../gcc/gcc/toplev.c:1972
#6 0x00002338 in _start (argc=6634700, argv=0x6268cc, envp=0x620000) at
/SourceCache/Csu/Csu-46/crt.c:267
#7 0x000021ac in start () at ../../gcc/libiberty/cp-demangle.c:651
(gdb)
dorit
|---------+---------------------------->
| | Aldy Hernandez |
| | <aldyh@redhat.com|
| | > |
| | |
| | 14/11/2004 14:09 |
|---------+---------------------------->
>------------------------------------------------------------------------------------------------------------------------|
| |
| To: Dorit Naishlos/Haifa/IBM@IBMIL |
| cc: David Edelsohn <dje@watson.ibm.com>, gcc@gcc.gnu.org |
| Subject: Re: RFC: PR14880 vec_duplicate or vec_select? |
>------------------------------------------------------------------------------------------------------------------------|
Well, since you're awake... :-)
Here is a patch rewriting the patterns. Visual inspection, and manual
testing yields the correct results. The middle-end problem was a typo
on my part, so there's nothing to fix there.
Can you give this a whirl to see if it addresses your concerns?
Thanks.
* config/rs6000/altivec.md ("altivec_vsplth"): Rewrite with
vec_duplicate.
(altivec_vspltb): Same.
(altivec_vspltw): Same.
(altivec_vspltisb): Same.
(altivec_vspltish): Same.
(altivec_vspltisw): Same.
(altivec_vspltisw_v4sf): Same.
(define_constants): Remove UNSPEC_VSPLTISB, UNSPEC_VSPLTISW,
UNSPEC_VSPLTISH.
Move "End of vector xor's" comment to the right place.
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.24
diff -c -p -r1.24 altivec.md
*** config/rs6000/altivec.md 7 Oct 2004 16:05:34 -0000
1.24
--- config/rs6000/altivec.md 14 Nov 2004 12:06:29 -0000
***************
*** 20,29 ****
;; MA 02111-1307, USA.
(define_constants
! [(UNSPEC_VSPLTISW 141)
! (UNSPEC_VSPLTISH 140)
! (UNSPEC_VSPLTISB 139)
! (UNSPEC_VCMPBFP 50)
(UNSPEC_VCMPEQUB 51)
(UNSPEC_VCMPEQUH 52)
(UNSPEC_VCMPEQUW 53)
--- 20,26 ----
;; MA 02111-1307, USA.
(define_constants
! [(UNSPEC_VCMPBFP 50)
(UNSPEC_VCMPEQUB 51)
(UNSPEC_VCMPEQUH 52)
(UNSPEC_VCMPEQUW 53)
***************
*** 1494,1552 ****
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
136))]
"TARGET_ALTIVEC"
"vspltb %0,%1,%2"
[(set_attr "type" "vecperm")])
- ;; End of vector xor's
(define_insn "altivec_vsplth"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
137))]
"TARGET_ALTIVEC"
"vsplth %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")]
138))]
"TARGET_ALTIVEC"
"vspltw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISB))]
"TARGET_ALTIVEC"
"vspltisb %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltish"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISH))]
"TARGET_ALTIVEC"
"vspltish %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
! UNSPEC_VSPLTISW))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")]
142))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
--- 1491,1557 ----
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
[(set_attr "type" "vecsimple")])
+ ;; End of vector xor's
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (vec_duplicate:V16QI
! (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
! (parallel
! [(match_operand:QI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vspltb %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vsplth"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (vec_duplicate:V8HI
! (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
! (parallel
! [(match_operand:HI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vsplth %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (vec_duplicate:V4SI
! (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
! (parallel
! [(match_operand:QI 2
"immediate_operand" "i")]))))]
"TARGET_ALTIVEC"
"vspltw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (vec_duplicate:V16QI
! (match_operand:QI 1 "immediate_operand" "i")))]
"TARGET_ALTIVEC"
"vspltisb %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltish"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (vec_duplicate:V8HI
! (sign_extend:HI (match_operand:QI 1 "immediate_operand"
"i"))))]
"TARGET_ALTIVEC"
"vspltish %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (vec_duplicate:V4SI
! (sign_extend:SI (match_operand:QI 1 "immediate_operand"
"i"))))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (vec_duplicate:V4SF
! (float:SF (sign_extend:SI
! (match_operand:QI 1 "immediate_operand"
"i")))))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])