[RFC] Rotating register allocation for swing modulo scheduling.

[Feng Wang <wf_cs at yahoo dot com>]

Hi, all
  I think software pipeline scheduling has a good beginning, though it still
has a long way to go. The swing modulo scheduling framework has been built. And
with the framework's support I think we can get enough information to implement
rotating register allocation. I want to contribute to add this feature, which
certainly will improve the SWP performance on ia64 platform. 
  I choices the article “Register Allocation for Modulo Scheduled Loops:
Strategies, Algorithms and Heuristics” (B.R.Rau, M.Lee, P.P.Tirumalai,
M.S.Schlansker, Computer Systems Laboratory, HPL-92-48, April, 1992) as the
guide. There are lots of problems needed advising.

  First, where should we allocate rotating registers?
  The SMS needs the allocation’s result to produce the prolog and epilog. In
the prolog we should assign EC, LC and RRB registers correctly. In the epilog
we should get the result from the rotating registers. Based on these, I think
we should perform rotating register allocation immediately after SMS. And the
registers’ lifetime and scheduling information such as II, SC, etc. are very
easy to get with the support of ddg. From the article I mentioned above, I
think it is not very hard to implement the rotating register allocation
algorithm. But now in gcc the maps of pseudo registers to hard registers are
all built in old/new register allocation. My question is that how we can map
partial local pseudo registers in the scheduling BEFORE register allocation?

  Second, how can we add a predicate register to a RTX? 
  Every insn in the same stage will be allocated a predict register. How can
the insns be converted to predicate insns with the specified hard predicate
register? I once looked through ifcvt.c (if_conversion), but it seemed that the
hard predicate register can not be used directly.

  Third, how can we deal with these loop-invariables?
  Maybe we can just leave them to global register allocation. At the same time
we should avoid the allocated rotating registers to be touched.

  The key difficulty is likely that the architecture of gcc does not fit the
interaction between scheduling and register allocation and seems not easy to
implement. But we need a beginning. 
  Any comment is appreciated.


Best regards,
Feng Wang
--
Creative Compiler Research Group.
National University of Defense Technology, China.

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