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GCC DFA Instruction Scheduler
- From: Sonawane Sachin Vijayku <sachinvs at cse dot iitb dot ac dot in>
- To: vmakarov at redhat dot com, gcc at gcc dot gnu dot org, gcc at gnu dot org
- Date: Fri, 1 Oct 2004 13:46:05 +0530 (IST)
- Subject: GCC DFA Instruction Scheduler
Hi all,
I am doing my M.Tech from IIT Bombay and some part of my Project is
related with GCC DFA based Instruction Scheduler.
I am desparately look for an implementation of this DFA based Instruction
Scheduler in GCC, which has been suggested by a paper titled as "The
finite state automaton based pipeline hazard recognizer and instruction
scheduler in GCC" by Vladimir N. Markarov.
Please let me know, which version of GCC has used this new model of
describing pipeline characteristics of which processors through .md file.
and also "First cycle multipass Instruction Scheduling" suggested in the
same paper has been implemented or not.
Thanks in advance
--
Regards.
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|Sachin Vijaykumar Sonawane|Hostel-12, R.No.-A107, |sachinvs@cse |
|M.Tech.-CSE-IITB, |Mobile-9819506594, |sachinvs@iitb |
|Roll.No.-03305039, |www.cse.iitb.ac.in/sachinvs|sachinvs2000@yahoo|
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