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Re: Register Allocation


On Tue, 21 Sep 2004, Adrian Strätling wrote:

> Hi,
> 
> I'm working on a target that does support up to 8 parallel instructions, 
> but they have to be grouped at compile time. The scheduler could do much 
> better than it currently does if there were less (output) depencies.
> 
> Is it possible to tell the register allocator not to reduce the register 
> count to the minimum?

I think you're trying to do this the wrong way.

The first scheduling pass is responsible for reordering the instructions
so the pseudo lifetimes are overlapping. 

This forces the register allocator to allocate the pseudos to different
hardware registers.

You need to look at why the first scheduling pass isn't reordering the
instructions on your target.

Toshi



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