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Re: More on memory barriers
On Wed, 15 Sep 2004 14:36:19 -0700, Richard Henderson <email@example.com> wrote:
> On Wed, Sep 15, 2004 at 05:28:27PM -0400, Jason Merrill wrote:
>> On the Alpha the problem has to do with its wacky cache-coherence rules,
>> but on other architectures the problem has everything to do with
>> speculation. If the memory model allows the processor to execute loads out
>> of order, you can run into the same problem by loading the contents of the
>> guarded object before the flag.
> For ppc this is only true if you use lwsync, correct?
> Using sync will kill speculation on other processors, correct?
I think that's what Geoff is saying.
> For i386 and ia64, speculation is canceled by cache probes.
OK. Can you point me at the relevant documentation?