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Using registers as a queue


I?m porting GCC to a new processor. I?m looking for ideas how to force
registers act like a queue. Example: let?s have instruction ADD that adds
two registers and puts the result in a register.

ADD R34,R5,R6?????? means R34=R5+R6

However, a second ADD (after the one above) *must* use specific registers
R35 as destination, and R7/R8 as sources:

ADD R35,R7,R8

If the third instruction is NEG, it *must* use registers R36 and R9:

NEG R36,R9

I know about a solution by using machine dependent reorganization
MACHINE_DEPENDENT_REORG(INSN), but this is a real headache. I wonder whether
there is a more elegant solution that is based on simpler/smaller changes in
target.md/.c/.h files.

Thanks in advance for any comments and ideas,
Pavel




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