RE: Multi-use register clobbering.

[Gyle Yearsley <gyearsley at zilog dot com>]

Maybe the question is worded wrong.  This particular processor
can operate on a 32-bit register as four bytes, two 16 bit half words
or a 32 bit word. I want gcc to be able to use any or all bytes in the
word for 8 or 16-bit operations. Normally if you define a 32 bit register in
gcc and specify it as QImode, HImode and SImode it can use the register in 
any of those modes. However it can only use it as a single 8 or 16 bit value
as shown in the diagram below.

	32 Bit register
|----------  Word  ----------|
|-- Not Used --| Half Word 0 |
|-- Not Used ---------|Byte 0|

If I define each as an individual register thus one word register can be
defined
as 7 registers (Four byte registers two word registers and the word itself).
If gcc 
uses any of the byte registers then one of the Half Words and the Word have
now been 
clobbered since that byte is part of the half word and word registers.
Somehow gcc
needs to know that if it uses one of the smaller registers it will clobber
the larger 
size registers.  

	32 Bit register
|----------  Word  ----------|	W0
| Half Word 1  | Half Word 0 |	H1		H0
| Byte 3|Byte 2|Byte 1|Byte 0|	B3	B2	B1	B0

Normally I would not worry about this, however this processor can only use
8-bit
values in the first four word registers. Thus gcc has only 4 QImode
registers. We
have seen spillage problems when using -O3 optimizations with only 4 QImode
registers. 

Thanks for your help,

Gyle

-----Original Message-----
From: James E Wilson [mailto:wilson@specifixinc.com]
Sent: Friday, August 13, 2004 7:37 PM
To: Gyle Yearsley
Cc: gcc@gcc.gnu.org
Subject: Re: Multi-use register clobbering.




Gyle Yearsley wrote:
> Is there any way to tell gcc that a processor can operate in byte
> mode on all four bytes of a 32 bit register? If any of the bytes are used
> then gcc would have to realize that the rest of the register was
clobbered. 

It isn't clear what you are trying to describe here.

If you are talking about a multimedia type instruction, then you use the 
vector modes.  V4QI is a 32-bit value composed of 4 1-byte elements.

If you are talking about bitfield insertion/extraction, then you can use 
zero_extract/sign_extract in the source/destination of a pattern to 
describe byte operations within a register.

There is also strict_lowpart, though this is really only used by some 
old ports like m68k, and this only works for the low byte.

There is also the possibility of using subregs, though this is probably 
best used only as a last resort.

I'm not sure what you mean when you say that the rest of the reg is 
clobbered when one byte is used.  Does that mean that if you write to 
one byte, the other 3 bytes end up with unknown values?  That seems like 
a poor hardware design.  Why bother having 4 of them if you can only use 
1 at a time?  I suspect you meant something else.

The compiler is smart enough to know that it can't put two values in the 
same register if they overlap, so there is no need to worry about the 
register being used for a 1 byte value and a 4 byte value at the same 
time.  That can't happen unless something is broken.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com