This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Inline functiion in GCC
- From: Venkatachala Upadhya <venkatu at samsung dot com>
- To: gcc at gcc dot gnu dot org
- Date: Fri, 06 Aug 2004 15:56:34 +0530
- Subject: Inline functiion in GCC
- Organization: Samsung
- Reply-to: venkatu at samsung dot com
Hello GCC people,
I am working on audio Codecs. I am using Linux 2.4.20 kernel on
ARM926EJS processor. The tool chain used is GCC 3.3.1 and the binutils
2.14. The codec code is optimised for ARMEJS priocessor using ADS suite
version 1.2. This optimised code is having C inline functions with
inline assembly statements. I have given here one inline C function with
inline assembly code for reference.
__inline Word16 add(Word16, Word16);
__inline Word16 add(Word16 x, Word16 y)
{
Word32 xs, ys;
Word16 rs;
__asm{
mov xs, x, lsl #16
mov ys, y, lsl #16
qadd xs, xs, ys
mov rs, xs, asr #16
}
return (rs);
}
I have ported the same code to GNU tool chain. I have used the
C-Language extention with Extended inline assembly feature, available in
GNU tool chain. The GNU port code is also reproduced here for reference.
__inline__ static int add(int, int) __attribute__ ((always_inline));
__inline__ static int add(int x, int y)
{
int xs, ys;
__asm__ __volatile__
(
"mov %3, %0, lsl #16 \n;"
"mov %4, %2, lsl #16 \n;"
"qadd %3, %3, %4 \n;"
"mov %0, %3, asr #16 \n;"
: "=r" (x)
: "0" (x), "r" (y), "r" (xs), "r" (ys)
) ;
return (x);
}
I have used this piece of code in the following example to study how the
inline is happening and the effectiveness of the inline.
#include <stdio.h>
#include <stdlib.h>
__inline__ static int add(int, int) __attribute__ ((always_inline));
__inline__ static int add(int x, int y)
{
int xs, ys;
__asm__ __volatile__
(
"mov %3, %0, lsl #16 \n;"
"mov %4, %2, lsl #16 \n;"
"qadd %3, %3, %4 \n;"
"mov %0, %3, asr #16 \n;"
: "=r" (x)
: "0" (x), "r" (y), "r" (xs), "r" (ys)
) ;
return (x);
}
int main (void)
{
int x=10, y=20, z=30;
int sum1, sum2, sum3;
sum1 = add (x, y);
sum2 = add (y, z);
sum3 = add (sum1, sum2);
printf("sum1 = %d sum2 = %d sum3 = %d\n", sum1, sum2, sum3);
}
Compilation option used is
arm_v4t_le-gcc -march=armv5te -msoft-float -finline-functions -Winline
-I. inline_test.c -o inline_out
I have generated the executable and got the object dump of this
executable with dis-assembly option (option -D). object dump command is
arm_v4t_le-objdump -D inline_out > inline_out_objdump
Using this inline_out_objdump file, I could see that the function main
has 285 ARM instructions. See the attached file inline_out_objdump.
Now I have converted this inline assembly to ARM assembly file as shown
below.
.global add
.code 32
.text
add:
mov r0, r0, lsl #16
mov r1, r1, lsl #16
qadd r0, r0, r1
mov r0, r0, asr #16
bx lr
.end
Now I wrote a test program as shown below.
#include <stdio.h>
#include <stdlib.h>
int main (void)
{
int x=10, y=20, z=30;
int sum1, sum2, sum3;
sum1 = add (x, y);
sum2 = add (y, z);
sum3 = add (sum1, sum2);
printf("sum1 = %d sum2 = %d sum3 = %d\n", sum1, sum2, sum3);
}
Compilation option used is
arm_v4t_le-gcc -march=armv5te -msoft-float -finline-functions -Winline
inline_add.s inline_test.c -o inline_out_as
I have got the object dump of this executable with dis-assembly option
(option -D). object dump command is
arm_v4t_le-objdump -D inline_out_as > as_objdump
I could see that the function main has 33 ARM instructions and add
function has 5 instructions. Since add is called three times in the
main, total number of instructions are 33+(3*5) = 48 instructions. See
the attached file as_objdump.
Now I find that there is a big increase in the number of ARM
instructions in the inline option compared to function call option. Also
I could notice that compiler has not used the set of registers available
(like r4, r5, ... r10) in the inline option, though it is free to use
it. Moreover, though we have 2 arguments in add, registers r2, r3 are
set to some value before entering the inline function. In case of
function call option. I guess, the compiler has used the registers
correctly. Is this the expected behaviour of GCC? I could not find the
advantage of using the inline in this case. In case of inline case, it
can also be seen that a number of un-necessary instructions are
generated, which can be avoided.
For this experiment, I have compared the GNU output with ADS suite 1.2,
for the same program. ADS output is much better compared to GNU.
Does any one have any comment on this? I am hoping that some one would
work on this to make the GCC better.
Please note that, I have added the number of instructions under the
label main and add to count the number of instructions in each case.
inline_out_as: file format elf32-littlearm
Disassembly of section .interp:
000080f4 <.interp>:
80f4: 62696c2f rsbvs r6, r9, #12032 ; 0x2f00
80f8: 2d646c2f stccsl 12, cr6, [r4, -#188]!
80fc: 756e696c strvcb r6, [lr, -#2412]!
8100: 6f732e78 swivs 0x00732e78
8104: Address 0x8104 is out of bounds.
Disassembly of section .note.ABI-tag:
00008108 <.note.ABI-tag>:
8108: 00000004 andeq r0, r0, r4
810c: 00000010 andeq r0, r0, r0, lsl r0
8110: 00000001 andeq r0, r0, r1
8114: 00554e47 subeqs r4, r5, r7, asr #28
8118: 00000000 andeq r0, r0, r0
811c: 00000002 andeq r0, r0, r2
8120: 00000004 andeq r0, r0, r4
8124: 00000011 andeq r0, r0, r1, lsl r0
Disassembly of section .hash:
00008128 <.hash>:
8128: 00000003 andeq r0, r0, r3
812c: 00000006 andeq r0, r0, r6
8130: 00000005 andeq r0, r0, r5
8134: 00000002 andeq r0, r0, r2
8138: 00000004 andeq r0, r0, r4
...
8148: 00000001 andeq r0, r0, r1
814c: 00000003 andeq r0, r0, r3
8150: 00000000 andeq r0, r0, r0
Disassembly of section .dynsym:
00008154 <.dynsym>:
...
8164: 00000021 andeq r0, r0, r1, lsr #32
8168: 00008278 andeq r8, r0, r8, ror r2
816c: 000001dc ldreqd r0, [r0], -ip
8170: 00000012 andeq r0, r0, r2, lsl r0
8174: 00000036 andeq r0, r0, r6, lsr r0
8178: 00008288 andeq r8, r0, r8, lsl #5
817c: 00000128 andeq r0, r0, r8, lsr #2
8180: 00000012 andeq r0, r0, r2, lsl r0
8184: 0000001a andeq r0, r0, sl, lsl r0
8188: 00008298 muleq r0, r8, r2
818c: 0000003c andeq r0, r0, ip, lsr r0
8190: 00000012 andeq r0, r0, r2, lsl r0
8194: 00000027 andeq r0, r0, r7, lsr #32
8198: 00008518 andeq r8, r0, r8, lsl r5
819c: 00000004 andeq r0, r0, r4
81a0: 000e0011 andeq r0, lr, r1, lsl r0
81a4: 00000001 andeq r0, r0, r1
...
81b0: 00000020 andeq r0, r0, r0, lsr #32
Disassembly of section .dynstr:
000081b4 <.dynstr>:
81b4: 675f5f00 ldrvsb r5, [pc, -r0, lsl #30]
81b8: 5f6e6f6d swipl 0x006e6f6d
81bc: 72617473 rsbvc r7, r1, #1929379840 ; 0x73000000
81c0: 005f5f74 subeqs r5, pc, r4, ror pc
81c4: 6362696c cmnvs r2, #1769472 ; 0x1b0000
81c8: 2e6f732e cdpcs 3, 6, cr7, cr15, cr14, {1}
81cc: 72700036 rsbvcs r0, r0, #54 ; 0x36
81d0: 66746e69 ldrvsbt r6, [r4], -r9, ror #28
81d4: 6f626100 swivs 0x00626100
81d8: 5f007472 swipl 0x00007472
81dc: 735f4f49 cmpvc pc, #292 ; 0x124
81e0: 6e696474 mcrvs 4, 3, r6, cr9, cr4, {3}
81e4: 6573755f ldrvsb r7, [r3, -#1375]!
81e8: 5f5f0064 swipl 0x005f0064
81ec: 6362696c cmnvs r2, #1769472 ; 0x1b0000
81f0: 6174735f cmnvs r4, pc, asr r3
81f4: 6d5f7472 cfldrdvs mvd7, [pc, -#456]
81f8: 006e6961 rsbeq r6, lr, r1, ror #18
81fc: 42494c47 submi r4, r9, #18176 ; 0x4700
8200: 2e325f43 cdpcs 15, 3, cr5, cr2, cr3, {2}
8204: Address 0x8204 is out of bounds.
Disassembly of section .gnu.version:
00008206 <.gnu.version>:
8206: 00020000 andeq r0, r2, r0
820a: 00020002 andeq r0, r2, r2
820e: 00000001 andeq r0, r0, r1
Disassembly of section .gnu.version_r:
00008214 <.gnu.version_r>:
8214: 00010001 andeq r0, r1, r1
8218: 00000010 andeq r0, r0, r0, lsl r0
821c: 00000010 andeq r0, r0, r0, lsl r0
8220: 00000000 andeq r0, r0, r0
8224: 0d696910 stceql 9, cr6, [r9, -#64]!
8228: 00020000 andeq r0, r2, r0
822c: 00000048 andeq r0, r0, r8, asr #32
8230: 00000000 andeq r0, r0, r0
Disassembly of section .rel.dyn:
00008234 <.rel.dyn>:
8234: 00010644 andeq r0, r1, r4, asr #12
8238: 00000515 andeq r0, r0, r5, lsl r5
Disassembly of section .rel.plt:
0000823c <.rel.plt>:
823c: 00010638 andeq r0, r1, r8, lsr r6
8240: 00000116 andeq r0, r0, r6, lsl r1
8244: 0001063c andeq r0, r1, ip, lsr r6
8248: 00000216 andeq r0, r0, r6, lsl r2
824c: 00010640 andeq r0, r1, r0, asr #12
8250: 00000316 andeq r0, r0, r6, lsl r3
Disassembly of section .init:
00008254 <_init>:
8254: e52de004 str lr, [sp, -#4]!
8258: eb000020 bl 82e0 <call_gmon_start>
825c: eb000045 bl 8378 <frame_dummy>
8260: eb000099 bl 84cc <__do_global_ctors_aux>
8264: e49df004 ldr pc, [sp], #4
Disassembly of section .plt:
00008268 <.plt>:
8268: e52de004 str lr, [sp, -#4]!
826c: e59fe010 ldr lr, [pc, #16] ; 8284 <_init+0x30>
8270: e08fe00e add lr, pc, lr
8274: e5bef008 ldr pc, [lr, #8]!
8278: e59fc004 ldr ip, [pc, #4] ; 8284 <_init+0x30>
827c: e08fc00c add ip, pc, ip
8280: e59cf000 ldr pc, [ip]
8284: 000083b4 streqh r8, [r0], -r4
8288: e59fc004 ldr ip, [pc, #4] ; 8294 <_init+0x40>
828c: e08fc00c add ip, pc, ip
8290: e59cf000 ldr pc, [ip]
8294: 000083a8 andeq r8, r0, r8, lsr #7
8298: e59fc004 ldr ip, [pc, #4] ; 82a4 <_init+0x50>
829c: e08fc00c add ip, pc, ip
82a0: e59cf000 ldr pc, [ip]
82a4: 0000839c muleq r0, ip, r3
Disassembly of section .text:
000082a8 <_start>:
82a8: e59fc024 ldr ip, [pc, #36] ; 82d4 <_start+0x2c>
82ac: e3a0b000 mov fp, #0 ; 0x0
82b0: e49d1004 ldr r1, [sp], #4
82b4: e1a0200d mov r2, sp
82b8: e52d2004 str r2, [sp, -#4]!
82bc: e52d0004 str r0, [sp, -#4]!
82c0: e59f0010 ldr r0, [pc, #16] ; 82d8 <_start+0x30>
82c4: e59f3010 ldr r3, [pc, #16] ; 82dc <_start+0x34>
82c8: e52dc004 str ip, [sp, -#4]!
82cc: ebffffed bl 8288 <_init+0x34>
82d0: ebffffe8 bl 8278 <_init+0x24>
82d4: 00008484 andeq r8, r0, r4, lsl #9
82d8: 000083a8 andeq r8, r0, r8, lsr #7
82dc: 00008440 andeq r8, r0, r0, asr #8
000082e0 <call_gmon_start>:
82e0: e92d4400 stmdb sp!, {sl, lr}
82e4: e59fa01c ldr sl, [pc, #28] ; 8308 <call_gmon_start+0x28>
82e8: e59f301c ldr r3, [pc, #28] ; 830c <call_gmon_start+0x2c>
82ec: e08fa00a add sl, pc, sl
82f0: e79a3003 ldr r3, [sl, r3]
82f4: e3530000 cmp r3, #0 ; 0x0
82f8: 08bd8400 ldmeqia sp!, {sl, pc}
82fc: e1a0e00f mov lr, pc
8300: e1a0f003 mov pc, r3
8304: e8bd8400 ldmia sp!, {sl, pc}
8308: 00008338 andeq r8, r0, r8, lsr r3
830c: 00000018 andeq r0, r0, r8, lsl r0
00008310 <__do_global_dtors_aux>:
8310: e92d4030 stmdb sp!, {r4, r5, lr}
8314: e59f504c ldr r5, [pc, #76] ; 8368 <__do_global_dtors_aux+0x58>
8318: e5d53000 ldrb r3, [r5]
831c: e3530000 cmp r3, #0 ; 0x0
8320: 18bd8030 ldmneia sp!, {r4, r5, pc}
8324: e59f4040 ldr r4, [pc, #64] ; 836c <__do_global_dtors_aux+0x5c>
8328: e5943000 ldr r3, [r4]
832c: e5932000 ldr r2, [r3]
8330: e3520000 cmp r2, #0 ; 0x0
8334: 0a000008 beq 835c <__do_global_dtors_aux+0x4c>
8338: e5943000 ldr r3, [r4]
833c: e2833004 add r3, r3, #4 ; 0x4
8340: e5843000 str r3, [r4]
8344: e1a0e00f mov lr, pc
8348: e1a0f002 mov pc, r2
834c: e5943000 ldr r3, [r4]
8350: e5932000 ldr r2, [r3]
8354: e3520000 cmp r2, #0 ; 0x0
8358: 1afffff6 bne 8338 <__do_global_dtors_aux+0x28>
835c: e3a03001 mov r3, #1 ; 0x1
8360: e5c53000 strb r3, [r5]
8364: e8bd8030 ldmia sp!, {r4, r5, pc}
8368: 00010648 andeq r0, r1, r8, asr #12
836c: 00010548 andeq r0, r1, r8, asr #10
00008370 <call___do_global_dtors_aux>:
8370: e52de004 str lr, [sp, -#4]!
8374: e49df004 ldr pc, [sp], #4
00008378 <frame_dummy>:
8378: e59f0018 ldr r0, [pc, #24] ; 8398 <frame_dummy+0x20>
837c: e5903000 ldr r3, [r0]
8380: e3530000 cmp r3, #0 ; 0x0
8384: 01a0f00e moveq pc, lr
8388: e59f300c ldr r3, [pc, #12] ; 839c <frame_dummy+0x24>
838c: e3530000 cmp r3, #0 ; 0x0
8390: 01a0f00e moveq pc, lr
8394: eaffdf19 b 0 <_init-0x8254>
8398: 00010628 andeq r0, r1, r8, lsr #12
839c: 00000000 andeq r0, r0, r0
000083a0 <call_frame_dummy>:
83a0: e52de004 str lr, [sp, -#4]!
83a4: e49df004 ldr pc, [sp], #4
000083a8 <main>:
83a8: e1a0c00d mov ip, sp
83ac: e92dd800 stmdb sp!, {fp, ip, lr, pc}
83b0: e24cb004 sub fp, ip, #4 ; 0x4
83b4: e24dd018 sub sp, sp, #24 ; 0x18
83b8: e3a0300a mov r3, #10 ; 0xa
83bc: e50b3010 str r3, [fp, -#16]
83c0: e3a03014 mov r3, #20 ; 0x14
83c4: e50b3014 str r3, [fp, -#20]
83c8: e3a0301e mov r3, #30 ; 0x1e
83cc: e50b3018 str r3, [fp, -#24]
83d0: e51b0010 ldr r0, [fp, -#16]
83d4: e51b1014 ldr r1, [fp, -#20]
83d8: eb000013 bl 842c <add>
83dc: e1a03000 mov r3, r0 --+
83e0: e50b301c str r3, [fp, -#28] --+ These two can be merged to 'str r0, [fp, -#28]
83e4: e51b0014 ldr r0, [fp, -#20]
83e8: e51b1018 ldr r1, [fp, -#24]
83ec: eb00000e bl 842c <add>
83f0: e1a03000 mov r3, r0 --+
83f4: e50b3020 str r3, [fp, -#32] --+ These two can be merged to 'str r0, [fp, -#32]
83f8: e51b001c ldr r0, [fp, -#28]
83fc: e51b1020 ldr r1, [fp, -#32]
8400: eb000009 bl 842c <add>
8404: e1a03000 mov r3, r0 --+
8408: e50b3024 str r3, [fp, -#36] --+ These two can be merged to 'str r0, [fp, -#36]
840c: e59f0014 ldr r0, [pc, #20] ; 8428 <main+0x80>
8410: e51b101c ldr r1, [fp, -#28]
8414: e51b2020 ldr r2, [fp, -#32]
8418: e51b3024 ldr r3, [fp, -#36]
841c: ebffff9d bl 8298 <_init+0x44>
8420: e1a00003 mov r0, r3
8424: e91ba800 ldmdb fp, {fp, sp, pc}
8428: 0000851c andeq r8, r0, ip, lsl r5
0000842c <add>:
842c: e1a00800 mov r0, r0, lsl #16
8430: e1a01801 mov r1, r1, lsl #16
8434: e1010050 qadd r0, r0, r1
8438: e1a00840 mov r0, r0, asr #16
843c: e12fff1e bx lr
00008440 <__libc_csu_init>:
8440: e92d4070 stmdb sp!, {r4, r5, r6, lr}
8444: ebffff82 bl 8254 <_init>
8448: e59f602c ldr r6, [pc, #44] ; 847c <__libc_csu_init+0x3c>
844c: e59f302c ldr r3, [pc, #44] ; 8480 <__libc_csu_init+0x40>
8450: e3a04000 mov r4, #0 ; 0x0
8454: e0663003 rsb r3, r6, r3
8458: e1540143 cmp r4, r3, asr #2
845c: 28bd8070 ldmcsia sp!, {r4, r5, r6, pc}
8460: e1a05003 mov r5, r3
8464: e1a0e00f mov lr, pc
8468: e796f104 ldr pc, [r6, r4, lsl #2]
846c: e2844001 add r4, r4, #1 ; 0x1
8470: e1540145 cmp r4, r5, asr #2
8474: 3afffffa bcc 8464 <__libc_csu_init+0x24>
8478: e8bd8070 ldmia sp!, {r4, r5, r6, pc}
847c: 00010540 andeq r0, r1, r0, asr #10
8480: 00010540 andeq r0, r1, r0, asr #10
00008484 <__libc_csu_fini>:
8484: e92d4030 stmdb sp!, {r4, r5, lr}
8488: e59f3034 ldr r3, [pc, #52] ; 84c4 <__libc_csu_fini+0x40>
848c: e59f5034 ldr r5, [pc, #52] ; 84c8 <__libc_csu_fini+0x44>
8490: e0653003 rsb r3, r5, r3
8494: e1a04143 mov r4, r3, asr #2
8498: e3540000 cmp r4, #0 ; 0x0
849c: e2444001 sub r4, r4, #1 ; 0x1
84a0: 1a000001 bne 84ac <__libc_csu_fini+0x28>
84a4: e8bd4030 ldmia sp!, {r4, r5, lr}
84a8: ea000017 b 850c <_fini>
84ac: e1a0e00f mov lr, pc
84b0: e795f104 ldr pc, [r5, r4, lsl #2]
84b4: e3540000 cmp r4, #0 ; 0x0
84b8: e2444001 sub r4, r4, #1 ; 0x1
84bc: 1afffffa bne 84ac <__libc_csu_fini+0x28>
84c0: eafffff7 b 84a4 <__libc_csu_fini+0x20>
84c4: 00010540 andeq r0, r1, r0, asr #10
84c8: 00010540 andeq r0, r1, r0, asr #10
000084cc <__do_global_ctors_aux>:
84cc: e92d4010 stmdb sp!, {r4, lr}
84d0: e59f3028 ldr r3, [pc, #40] ; 8500 <__do_global_ctors_aux+0x34>
84d4: e5132004 ldr r2, [r3, -#4]
84d8: e2434004 sub r4, r3, #4 ; 0x4
84dc: e3720001 cmn r2, #1 ; 0x1
84e0: 08bd8010 ldmeqia sp!, {r4, pc}
84e4: e1a03002 mov r3, r2
84e8: e1a0e00f mov lr, pc
84ec: e1a0f003 mov pc, r3
84f0: e5343004 ldr r3, [r4, -#4]!
84f4: e3730001 cmn r3, #1 ; 0x1
84f8: 1afffffa bne 84e8 <__do_global_ctors_aux+0x1c>
84fc: e8bd8010 ldmia sp!, {r4, pc}
8500: 0001061c andeq r0, r1, ip, lsl r6
00008504 <call___do_global_ctors_aux>:
8504: e52de004 str lr, [sp, -#4]!
8508: e49df004 ldr pc, [sp], #4
Disassembly of section .fini:
0000850c <_fini>:
850c: e52de004 str lr, [sp, -#4]!
8510: ebffff7e bl 8310 <__do_global_dtors_aux>
8514: e49df004 ldr pc, [sp], #4
Disassembly of section .rodata:
00008518 <_IO_stdin_used>:
8518: 00020001 andeq r0, r2, r1
851c: 316d7573 cmncc sp, r3, ror r5
8520: 25203d20 strcs r3, [r0, -#3360]!
8524: 73202064 teqvc r0, #100 ; 0x64
8528: 20326d75 eorcss r6, r2, r5, ror sp
852c: 6425203d strvst r2, [r5], -#61
8530: 75732020 ldrvcb r2, [r3, -#32]!
8534: 3d20336d stccc 3, cr3, [r0, -#436]!
8538: 0a642520 beq 19119c0 <__bss_end__+0x1901374>
853c: 00000000 andeq r0, r0, r0
Disassembly of section .data:
00010540 <__data_start>:
10540: 00000000 andeq r0, r0, r0
00010544 <__dso_handle>:
10544: 00000000 andeq r0, r0, r0
00010548 <p.0>:
10548: 00010624 andeq r0, r1, r4, lsr #12
Disassembly of section .eh_frame:
0001054c <__FRAME_END__>:
1054c: 00000000 andeq r0, r0, r0
Disassembly of section .dynamic:
00010550 <_DYNAMIC>:
10550: 00000001 andeq r0, r0, r1
10554: 00000010 andeq r0, r0, r0, lsl r0
10558: 0000000c andeq r0, r0, ip
1055c: 00008254 andeq r8, r0, r4, asr r2
10560: 0000000d andeq r0, r0, sp
10564: 0000850c andeq r8, r0, ip, lsl #10
10568: 00000004 andeq r0, r0, r4
1056c: 00008128 andeq r8, r0, r8, lsr #2
10570: 00000005 andeq r0, r0, r5
10574: 000081b4 streqh r8, [r0], -r4
10578: 00000006 andeq r0, r0, r6
1057c: 00008154 andeq r8, r0, r4, asr r1
10580: 0000000a andeq r0, r0, sl
10584: 00000052 andeq r0, r0, r2, asr r0
10588: 0000000b andeq r0, r0, fp
1058c: 00000010 andeq r0, r0, r0, lsl r0
10590: 00000015 andeq r0, r0, r5, lsl r0
10594: 00000000 andeq r0, r0, r0
10598: 00000003 andeq r0, r0, r3
1059c: 0001062c andeq r0, r1, ip, lsr #12
105a0: 00000002 andeq r0, r0, r2
105a4: 00000018 andeq r0, r0, r8, lsl r0
105a8: 00000014 andeq r0, r0, r4, lsl r0
105ac: 00000011 andeq r0, r0, r1, lsl r0
105b0: 00000017 andeq r0, r0, r7, lsl r0
105b4: 0000823c andeq r8, r0, ip, lsr r2
105b8: 00000011 andeq r0, r0, r1, lsl r0
105bc: 00008234 andeq r8, r0, r4, lsr r2
105c0: 00000012 andeq r0, r0, r2, lsl r0
105c4: 00000008 andeq r0, r0, r8
105c8: 00000013 andeq r0, r0, r3, lsl r0
105cc: 00000008 andeq r0, r0, r8
105d0: 6ffffffe swivs 0x00fffffe
105d4: 00008214 andeq r8, r0, r4, lsl r2
105d8: 6fffffff swivs 0x00ffffff
105dc: 00000001 andeq r0, r0, r1
105e0: 6ffffff0 swivs 0x00fffff0
105e4: 00008206 andeq r8, r0, r6, lsl #4
...
Disassembly of section .ctors:
00010618 <__CTOR_LIST__>:
10618: ffffffff swinv 0x00ffffff
0001061c <__CTOR_END__>:
1061c: 00000000 andeq r0, r0, r0
Disassembly of section .dtors:
00010620 <__DTOR_LIST__>:
10620: ffffffff swinv 0x00ffffff
00010624 <__DTOR_END__>:
10624: 00000000 andeq r0, r0, r0
Disassembly of section .jcr:
00010628 <__JCR_END__>:
10628: 00000000 andeq r0, r0, r0
Disassembly of section .got:
0001062c <_GLOBAL_OFFSET_TABLE_>:
1062c: 00010550 andeq r0, r1, r0, asr r5
...
10638: 00008268 andeq r8, r0, r8, ror #4
1063c: 00008268 andeq r8, r0, r8, ror #4
10640: 00008268 andeq r8, r0, r8, ror #4
10644: 00000000 andeq r0, r0, r0
inline_out: file format elf32-littlearm
Disassembly of section .interp:
000080f4 <.interp>:
80f4: 62696c2f rsbvs r6, r9, #12032 ; 0x2f00
80f8: 2d646c2f stccsl 12, cr6, [r4, -#188]!
80fc: 756e696c strvcb r6, [lr, -#2412]!
8100: 6f732e78 swivs 0x00732e78
8104: Address 0x8104 is out of bounds.
Disassembly of section .note.ABI-tag:
00008108 <.note.ABI-tag>:
8108: 00000004 andeq r0, r0, r4
810c: 00000010 andeq r0, r0, r0, lsl r0
8110: 00000001 andeq r0, r0, r1
8114: 00554e47 subeqs r4, r5, r7, asr #28
8118: 00000000 andeq r0, r0, r0
811c: 00000002 andeq r0, r0, r2
8120: 00000004 andeq r0, r0, r4
8124: 00000011 andeq r0, r0, r1, lsl r0
Disassembly of section .hash:
00008128 <.hash>:
8128: 00000003 andeq r0, r0, r3
812c: 00000006 andeq r0, r0, r6
8130: 00000005 andeq r0, r0, r5
8134: 00000002 andeq r0, r0, r2
8138: 00000004 andeq r0, r0, r4
...
8148: 00000001 andeq r0, r0, r1
814c: 00000003 andeq r0, r0, r3
8150: 00000000 andeq r0, r0, r0
Disassembly of section .dynsym:
00008154 <.dynsym>:
...
8164: 00000021 andeq r0, r0, r1, lsr #32
8168: 00008278 andeq r8, r0, r8, ror r2
816c: 000001dc ldreqd r0, [r0], -ip
8170: 00000012 andeq r0, r0, r2, lsl r0
8174: 00000036 andeq r0, r0, r6, lsr r0
8178: 00008288 andeq r8, r0, r8, lsl #5
817c: 00000128 andeq r0, r0, r8, lsr #2
8180: 00000012 andeq r0, r0, r2, lsl r0
8184: 0000001a andeq r0, r0, sl, lsl r0
8188: 00008298 muleq r0, r8, r2
818c: 0000003c andeq r0, r0, ip, lsr r0
8190: 00000012 andeq r0, r0, r2, lsl r0
8194: 00000027 andeq r0, r0, r7, lsr #32
8198: 000085a0 andeq r8, r0, r0, lsr #11
819c: 00000004 andeq r0, r0, r4
81a0: 000e0011 andeq r0, lr, r1, lsl r0
81a4: 00000001 andeq r0, r0, r1
...
81b0: 00000020 andeq r0, r0, r0, lsr #32
Disassembly of section .dynstr:
000081b4 <.dynstr>:
81b4: 675f5f00 ldrvsb r5, [pc, -r0, lsl #30]
81b8: 5f6e6f6d swipl 0x006e6f6d
81bc: 72617473 rsbvc r7, r1, #1929379840 ; 0x73000000
81c0: 005f5f74 subeqs r5, pc, r4, ror pc
81c4: 6362696c cmnvs r2, #1769472 ; 0x1b0000
81c8: 2e6f732e cdpcs 3, 6, cr7, cr15, cr14, {1}
81cc: 72700036 rsbvcs r0, r0, #54 ; 0x36
81d0: 66746e69 ldrvsbt r6, [r4], -r9, ror #28
81d4: 6f626100 swivs 0x00626100
81d8: 5f007472 swipl 0x00007472
81dc: 735f4f49 cmpvc pc, #292 ; 0x124
81e0: 6e696474 mcrvs 4, 3, r6, cr9, cr4, {3}
81e4: 6573755f ldrvsb r7, [r3, -#1375]!
81e8: 5f5f0064 swipl 0x005f0064
81ec: 6362696c cmnvs r2, #1769472 ; 0x1b0000
81f0: 6174735f cmnvs r4, pc, asr r3
81f4: 6d5f7472 cfldrdvs mvd7, [pc, -#456]
81f8: 006e6961 rsbeq r6, lr, r1, ror #18
81fc: 42494c47 submi r4, r9, #18176 ; 0x4700
8200: 2e325f43 cdpcs 15, 3, cr5, cr2, cr3, {2}
8204: Address 0x8204 is out of bounds.
Disassembly of section .gnu.version:
00008206 <.gnu.version>:
8206: 00020000 andeq r0, r2, r0
820a: 00020002 andeq r0, r2, r2
820e: 00000001 andeq r0, r0, r1
Disassembly of section .gnu.version_r:
00008214 <.gnu.version_r>:
8214: 00010001 andeq r0, r1, r1
8218: 00000010 andeq r0, r0, r0, lsl r0
821c: 00000010 andeq r0, r0, r0, lsl r0
8220: 00000000 andeq r0, r0, r0
8224: 0d696910 stceql 9, cr6, [r9, -#64]!
8228: 00020000 andeq r0, r2, r0
822c: 00000048 andeq r0, r0, r8, asr #32
8230: 00000000 andeq r0, r0, r0
Disassembly of section .rel.dyn:
00008234 <.rel.dyn>:
8234: 000106cc andeq r0, r1, ip, asr #13
8238: 00000515 andeq r0, r0, r5, lsl r5
Disassembly of section .rel.plt:
0000823c <.rel.plt>:
823c: 000106c0 andeq r0, r1, r0, asr #13
8240: 00000116 andeq r0, r0, r6, lsl r1
8244: 000106c4 andeq r0, r1, r4, asr #13
8248: 00000216 andeq r0, r0, r6, lsl r2
824c: 000106c8 andeq r0, r1, r8, asr #13
8250: 00000316 andeq r0, r0, r6, lsl r3
Disassembly of section .init:
00008254 <_init>:
8254: e52de004 str lr, [sp, -#4]!
8258: eb000020 bl 82e0 <call_gmon_start>
825c: eb000045 bl 8378 <frame_dummy>
8260: eb0000bb bl 8554 <__do_global_ctors_aux>
8264: e49df004 ldr pc, [sp], #4
Disassembly of section .plt:
00008268 <.plt>:
8268: e52de004 str lr, [sp, -#4]!
826c: e59fe010 ldr lr, [pc, #16] ; 8284 <_init+0x30>
8270: e08fe00e add lr, pc, lr
8274: e5bef008 ldr pc, [lr, #8]!
8278: e59fc004 ldr ip, [pc, #4] ; 8284 <_init+0x30>
827c: e08fc00c add ip, pc, ip
8280: e59cf000 ldr pc, [ip]
8284: 0000843c andeq r8, r0, ip, lsr r4
8288: e59fc004 ldr ip, [pc, #4] ; 8294 <_init+0x40>
828c: e08fc00c add ip, pc, ip
8290: e59cf000 ldr pc, [ip]
8294: 00008430 andeq r8, r0, r0, lsr r4
8298: e59fc004 ldr ip, [pc, #4] ; 82a4 <_init+0x50>
829c: e08fc00c add ip, pc, ip
82a0: e59cf000 ldr pc, [ip]
82a4: 00008424 andeq r8, r0, r4, lsr #8
Disassembly of section .text:
000082a8 <_start>:
82a8: e59fc024 ldr ip, [pc, #36] ; 82d4 <_start+0x2c>
82ac: e3a0b000 mov fp, #0 ; 0x0
82b0: e49d1004 ldr r1, [sp], #4
82b4: e1a0200d mov r2, sp
82b8: e52d2004 str r2, [sp, -#4]!
82bc: e52d0004 str r0, [sp, -#4]!
82c0: e59f0010 ldr r0, [pc, #16] ; 82d8 <_start+0x30>
82c4: e59f3010 ldr r3, [pc, #16] ; 82dc <_start+0x34>
82c8: e52dc004 str ip, [sp, -#4]!
82cc: ebffffed bl 8288 <_init+0x34>
82d0: ebffffe8 bl 8278 <_init+0x24>
82d4: 0000850c andeq r8, r0, ip, lsl #10
82d8: 000083a8 andeq r8, r0, r8, lsr #7
82dc: 000084c8 andeq r8, r0, r8, asr #9
000082e0 <call_gmon_start>:
82e0: e92d4400 stmdb sp!, {sl, lr}
82e4: e59fa01c ldr sl, [pc, #28] ; 8308 <call_gmon_start+0x28>
82e8: e59f301c ldr r3, [pc, #28] ; 830c <call_gmon_start+0x2c>
82ec: e08fa00a add sl, pc, sl
82f0: e79a3003 ldr r3, [sl, r3]
82f4: e3530000 cmp r3, #0 ; 0x0
82f8: 08bd8400 ldmeqia sp!, {sl, pc}
82fc: e1a0e00f mov lr, pc
8300: e1a0f003 mov pc, r3
8304: e8bd8400 ldmia sp!, {sl, pc}
8308: 000083c0 andeq r8, r0, r0, asr #7
830c: 00000018 andeq r0, r0, r8, lsl r0
00008310 <__do_global_dtors_aux>:
8310: e92d4030 stmdb sp!, {r4, r5, lr}
8314: e59f504c ldr r5, [pc, #76] ; 8368 <__do_global_dtors_aux+0x58>
8318: e5d53000 ldrb r3, [r5]
831c: e3530000 cmp r3, #0 ; 0x0
8320: 18bd8030 ldmneia sp!, {r4, r5, pc}
8324: e59f4040 ldr r4, [pc, #64] ; 836c <__do_global_dtors_aux+0x5c>
8328: e5943000 ldr r3, [r4]
832c: e5932000 ldr r2, [r3]
8330: e3520000 cmp r2, #0 ; 0x0
8334: 0a000008 beq 835c <__do_global_dtors_aux+0x4c>
8338: e5943000 ldr r3, [r4]
833c: e2833004 add r3, r3, #4 ; 0x4
8340: e5843000 str r3, [r4]
8344: e1a0e00f mov lr, pc
8348: e1a0f002 mov pc, r2
834c: e5943000 ldr r3, [r4]
8350: e5932000 ldr r2, [r3]
8354: e3520000 cmp r2, #0 ; 0x0
8358: 1afffff6 bne 8338 <__do_global_dtors_aux+0x28>
835c: e3a03001 mov r3, #1 ; 0x1
8360: e5c53000 strb r3, [r5]
8364: e8bd8030 ldmia sp!, {r4, r5, pc}
8368: 000106d0 ldreqd r0, [r1], -r0
836c: 000105d0 ldreqd r0, [r1], -r0
00008370 <call___do_global_dtors_aux>:
8370: e52de004 str lr, [sp, -#4]!
8374: e49df004 ldr pc, [sp], #4
00008378 <frame_dummy>:
8378: e59f0018 ldr r0, [pc, #24] ; 8398 <frame_dummy+0x20>
837c: e5903000 ldr r3, [r0]
8380: e3530000 cmp r3, #0 ; 0x0
8384: 01a0f00e moveq pc, lr
8388: e59f300c ldr r3, [pc, #12] ; 839c <frame_dummy+0x24>
838c: e3530000 cmp r3, #0 ; 0x0
8390: 01a0f00e moveq pc, lr
8394: eaffdf19 b 0 <_init-0x8254>
8398: 000106b0 streqh r0, [r1], -r0
839c: 00000000 andeq r0, r0, r0
000083a0 <call_frame_dummy>:
83a0: e52de004 str lr, [sp, -#4]!
83a4: e49df004 ldr pc, [sp], #4
000083a8 <main>:
83a8: e1a0c00d mov ip, sp
83ac: e92dd800 stmdb sp!, {fp, ip, lr, pc}
83b0: e24cb004 sub fp, ip, #4 ; 0x4
83b4: e24dd02c sub sp, sp, #44 ; 0x2c
83b8: e3a0300a mov r3, #10 ; 0xa
83bc: e50b3010 str r3, [fp, -#16]
83c0: e3a03014 mov r3, #20 ; 0x14
83c4: e50b3014 str r3, [fp, -#20]
83c8: e3a0301e mov r3, #30 ; 0x1e
83cc: e50b3018 str r3, [fp, -#24]
83d0: e51b3010 ldr r3, [fp, -#16] --+
83d4: e50b3028 str r3, [fp, -#40] + Do not know why these statements ? Can be optimised
83d8: e51b3014 ldr r3, [fp, -#20] +
83dc: e50b302c str r3, [fp, -#44] --+
83e0: e51b0028 ldr r0, [fp, -#40]
83e4: e51b102c ldr r1, [fp, -#44]
83e8: e51b2034 ldr r2, [fp, -#52] --+
83ec: e51b3038 ldr r3, [fp, -#56] --+ Though there are only 2 inputs to add, r2 and r3 are loaded
83f0: e1a02800 mov r2, r0, lsl #16
83f4: e1a03801 mov r3, r1, lsl #16
83f8: e1032052 qadd r2, r2, r3
83fc: e1a00842 mov r0, r2, asr #16
8400: e1a03000 mov r3, r0 --+
8404: e50b3028 str r3, [fp, -#40] --+ Can be replaced with 'str r0, [fp -#28]'
8408: e51b3028 ldr r3, [fp, -#40] --+
840c: e50b3030 str r3, [fp, -#48] +
8410: e51b3030 ldr r3, [fp, -#48] +
8414: e50b301c str r3, [fp, -#28] +
8418: e51b3014 ldr r3, [fp, -#20] +
841c: e50b3038 str r3, [fp, -#56] +
8420: e51b3018 ldr r3, [fp, -#24] + Do not know why these statements ? Can be optimised
8424: e50b3034 str r3, [fp, -#52] --+
8428: e51b0038 ldr r0, [fp, -#56]
842c: e51b1034 ldr r1, [fp, -#52]
8430: e51b202c ldr r2, [fp, -#44]
8434: e51b3028 ldr r3, [fp, -#40]
8438: e1a02800 mov r2, r0, lsl #16
843c: e1a03801 mov r3, r1, lsl #16
8440: e1032052 qadd r2, r2, r3
8444: e1a00842 mov r0, r2, asr #16
8448: e1a03000 mov r3, r0 --+
844c: e50b3038 str r3, [fp, -#56] --+ Can be replaced with 'str r0, [fp -#32]'
8450: e51b3038 ldr r3, [fp, -#56] --+
8454: e50b3030 str r3, [fp, -#48] +
8458: e51b3030 ldr r3, [fp, -#48] +
845c: e50b3020 str r3, [fp, -#32] +
8460: e51b301c ldr r3, [fp, -#28] +
8464: e50b3038 str r3, [fp, -#56] + Do not know why these statements ? Can be optimised
8468: e51b3020 ldr r3, [fp, -#32] +
846c: e50b3034 str r3, [fp, -#52] --+
8470: e51b0038 ldr r0, [fp, -#56]
8474: e51b1034 ldr r1, [fp, -#52]
8478: e51b202c ldr r2, [fp, -#44]
847c: e51b3028 ldr r3, [fp, -#40]
8480: e1a02800 mov r2, r0, lsl #16
8484: e1a03801 mov r3, r1, lsl #16
8488: e1032052 qadd r2, r2, r3
848c: e1a00842 mov r0, r2, asr #16
8490: e1a03000 mov r3, r0 --+
8494: e50b3038 str r3, [fp, -#56] --+ Can be replaced with 'str r0, [fp -#36]'
8498: e51b3038 ldr r3, [fp, -#56] --+
849c: e50b3030 str r3, [fp, -#48] + Do not know why these statements ? Can be optimised
84a0: e51b3030 ldr r3, [fp, -#48] +
84a4: e50b3024 str r3, [fp, -#36] --+
84a8: e59f0014 ldr r0, [pc, #20] ; 84c4 <main+0x11c>
84ac: e51b101c ldr r1, [fp, -#28]
84b0: e51b2020 ldr r2, [fp, -#32]
84b4: e51b3024 ldr r3, [fp, -#36]
84b8: ebffff76 bl 8298 <_init+0x44>
84bc: e1a00003 mov r0, r3
84c0: e91ba800 ldmdb fp, {fp, sp, pc}
84c4: 000085a4 andeq r8, r0, r4, lsr #11
000084c8 <__libc_csu_init>:
84c8: e92d4070 stmdb sp!, {r4, r5, r6, lr}
84cc: ebffff60 bl 8254 <_init>
84d0: e59f602c ldr r6, [pc, #44] ; 8504 <__libc_csu_init+0x3c>
84d4: e59f302c ldr r3, [pc, #44] ; 8508 <__libc_csu_init+0x40>
84d8: e3a04000 mov r4, #0 ; 0x0
84dc: e0663003 rsb r3, r6, r3
84e0: e1540143 cmp r4, r3, asr #2
84e4: 28bd8070 ldmcsia sp!, {r4, r5, r6, pc}
84e8: e1a05003 mov r5, r3
84ec: e1a0e00f mov lr, pc
84f0: e796f104 ldr pc, [r6, r4, lsl #2]
84f4: e2844001 add r4, r4, #1 ; 0x1
84f8: e1540145 cmp r4, r5, asr #2
84fc: 3afffffa bcc 84ec <__libc_csu_init+0x24>
8500: e8bd8070 ldmia sp!, {r4, r5, r6, pc}
8504: 000105c8 andeq r0, r1, r8, asr #11
8508: 000105c8 andeq r0, r1, r8, asr #11
0000850c <__libc_csu_fini>:
850c: e92d4030 stmdb sp!, {r4, r5, lr}
8510: e59f3034 ldr r3, [pc, #52] ; 854c <__libc_csu_fini+0x40>
8514: e59f5034 ldr r5, [pc, #52] ; 8550 <__libc_csu_fini+0x44>
8518: e0653003 rsb r3, r5, r3
851c: e1a04143 mov r4, r3, asr #2
8520: e3540000 cmp r4, #0 ; 0x0
8524: e2444001 sub r4, r4, #1 ; 0x1
8528: 1a000001 bne 8534 <__libc_csu_fini+0x28>
852c: e8bd4030 ldmia sp!, {r4, r5, lr}
8530: ea000017 b 8594 <_fini>
8534: e1a0e00f mov lr, pc
8538: e795f104 ldr pc, [r5, r4, lsl #2]
853c: e3540000 cmp r4, #0 ; 0x0
8540: e2444001 sub r4, r4, #1 ; 0x1
8544: 1afffffa bne 8534 <__libc_csu_fini+0x28>
8548: eafffff7 b 852c <__libc_csu_fini+0x20>
854c: 000105c8 andeq r0, r1, r8, asr #11
8550: 000105c8 andeq r0, r1, r8, asr #11
00008554 <__do_global_ctors_aux>:
8554: e92d4010 stmdb sp!, {r4, lr}
8558: e59f3028 ldr r3, [pc, #40] ; 8588 <__do_global_ctors_aux+0x34>
855c: e5132004 ldr r2, [r3, -#4]
8560: e2434004 sub r4, r3, #4 ; 0x4
8564: e3720001 cmn r2, #1 ; 0x1
8568: 08bd8010 ldmeqia sp!, {r4, pc}
856c: e1a03002 mov r3, r2
8570: e1a0e00f mov lr, pc
8574: e1a0f003 mov pc, r3
8578: e5343004 ldr r3, [r4, -#4]!
857c: e3730001 cmn r3, #1 ; 0x1
8580: 1afffffa bne 8570 <__do_global_ctors_aux+0x1c>
8584: e8bd8010 ldmia sp!, {r4, pc}
8588: 000106a4 andeq r0, r1, r4, lsr #13
0000858c <call___do_global_ctors_aux>:
858c: e52de004 str lr, [sp, -#4]!
8590: e49df004 ldr pc, [sp], #4
Disassembly of section .fini:
00008594 <_fini>:
8594: e52de004 str lr, [sp, -#4]!
8598: ebffff5c bl 8310 <__do_global_dtors_aux>
859c: e49df004 ldr pc, [sp], #4
Disassembly of section .rodata:
000085a0 <_IO_stdin_used>:
85a0: 00020001 andeq r0, r2, r1
85a4: 316d7573 cmncc sp, r3, ror r5
85a8: 25203d20 strcs r3, [r0, -#3360]!
85ac: 73202064 teqvc r0, #100 ; 0x64
85b0: 20326d75 eorcss r6, r2, r5, ror sp
85b4: 6425203d strvst r2, [r5], -#61
85b8: 75732020 ldrvcb r2, [r3, -#32]!
85bc: 3d20336d stccc 3, cr3, [r0, -#436]!
85c0: 0a642520 beq 1911a48 <__bss_end__+0x1901374>
85c4: 00000000 andeq r0, r0, r0
Disassembly of section .data:
000105c8 <__data_start>:
105c8: 00000000 andeq r0, r0, r0
000105cc <__dso_handle>:
105cc: 00000000 andeq r0, r0, r0
000105d0 <p.0>:
105d0: 000106ac andeq r0, r1, ip, lsr #13
Disassembly of section .eh_frame:
000105d4 <__FRAME_END__>:
105d4: 00000000 andeq r0, r0, r0
Disassembly of section .dynamic:
000105d8 <_DYNAMIC>:
105d8: 00000001 andeq r0, r0, r1
105dc: 00000010 andeq r0, r0, r0, lsl r0
105e0: 0000000c andeq r0, r0, ip
105e4: 00008254 andeq r8, r0, r4, asr r2
105e8: 0000000d andeq r0, r0, sp
105ec: 00008594 muleq r0, r4, r5
105f0: 00000004 andeq r0, r0, r4
105f4: 00008128 andeq r8, r0, r8, lsr #2
105f8: 00000005 andeq r0, r0, r5
105fc: 000081b4 streqh r8, [r0], -r4
10600: 00000006 andeq r0, r0, r6
10604: 00008154 andeq r8, r0, r4, asr r1
10608: 0000000a andeq r0, r0, sl
1060c: 00000052 andeq r0, r0, r2, asr r0
10610: 0000000b andeq r0, r0, fp
10614: 00000010 andeq r0, r0, r0, lsl r0
10618: 00000015 andeq r0, r0, r5, lsl r0
1061c: 00000000 andeq r0, r0, r0
10620: 00000003 andeq r0, r0, r3
10624: 000106b4 streqh r0, [r1], -r4
10628: 00000002 andeq r0, r0, r2
1062c: 00000018 andeq r0, r0, r8, lsl r0
10630: 00000014 andeq r0, r0, r4, lsl r0
10634: 00000011 andeq r0, r0, r1, lsl r0
10638: 00000017 andeq r0, r0, r7, lsl r0
1063c: 0000823c andeq r8, r0, ip, lsr r2
10640: 00000011 andeq r0, r0, r1, lsl r0
10644: 00008234 andeq r8, r0, r4, lsr r2
10648: 00000012 andeq r0, r0, r2, lsl r0
1064c: 00000008 andeq r0, r0, r8
10650: 00000013 andeq r0, r0, r3, lsl r0
10654: 00000008 andeq r0, r0, r8
10658: 6ffffffe swivs 0x00fffffe
1065c: 00008214 andeq r8, r0, r4, lsl r2
10660: 6fffffff swivs 0x00ffffff
10664: 00000001 andeq r0, r0, r1
10668: 6ffffff0 swivs 0x00fffff0
1066c: 00008206 andeq r8, r0, r6, lsl #4
...
Disassembly of section .ctors:
000106a0 <__CTOR_LIST__>:
106a0: ffffffff swinv 0x00ffffff
000106a4 <__CTOR_END__>:
106a4: 00000000 andeq r0, r0, r0
Disassembly of section .dtors:
000106a8 <__DTOR_LIST__>:
106a8: ffffffff swinv 0x00ffffff
000106ac <__DTOR_END__>:
106ac: 00000000 andeq r0, r0, r0
Disassembly of section .jcr:
000106b0 <__JCR_END__>:
106b0: 00000000 andeq r0, r0, r0
Disassembly of section .got:
000106b4 <_GLOBAL_OFFSET_TABLE_>:
106b4: 000105d8 ldreqd r0, [r1], -r8
...
106c0: 00008268 andeq r8, r0, r8, ror #4
106c4: 00008268 andeq r8, r0, r8, ror #4
106c8: 00008268 andeq r8, r0, r8, ror #4
106cc: 00000000 andeq r0, r0, r0