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Re: "GCC needs a patch to avoid the EM64T instruction Intel screwedup"
- From: Andi Kleen <ak at muc dot de>
- To: Andreas Jaeger <aj at suse dot de>
- Cc: toon at moene dot indiv dot nluug dot nl, gcc at gcc dot gnu dot org
- Date: Fri, 16 Jul 2004 06:53:15 +0200
- Subject: Re: "GCC needs a patch to avoid the EM64T instruction Intel screwedup"
- References: <40F6FA56.4050107@moene.indiv.nluug.nl><m3k6x4bu71.fsf@gromit.moeb>
Andreas Jaeger <aj@suse.de> writes:
> Toon Moene <toon@moene.indiv.nluug.nl> writes:
>
>> Just read the following on the Beowulf mailing list - perhaps it is
>> known here already and I just didn't parse the gcc-patches mails that
>> talked about EM64T correctly. So just in case:
>
> AMD64 implements the AMD NOW! instructions including a prefetch
> instruction that was previously used by GCC. This has been removed
> already some time ago from AMD64 code so that the code runs on both
> cpus. Other than that, I'm not aware of any issue,
There are a few more differences, although they would be relatively
unlikely for a compiler to generate directly: e.g. bsr/bsr with 32bit
operand size behave slightly different. And LAHF works on AMD 64bit
mode and doesn't on Intel.
The main issue is probably that P4 prefers completely different
code.
-Andi