This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[apple-ppc] Inserting copies on backarc when exiting from ssa


With a recent patch to apple-ppc we now generate the following sequence
when vectorizing misaligned loads in a loop (e.g. tree-ssa-vect-27.c):

      v0_init = load_vector_from_first_address
Loop:
      v0 = phi (v0_init, v1)
      v1 = load_vector_from_next_address
      v2 = extract (v0, v1)
      <the desired misaligned vector data now exists in v2>
      goto Loop

The problem is that when we get out of SSA, the copy v0=v1 is placed on the
backarc, and stays there. The final altivec assembly looks like:

L14:
        addi r9,r1,580
        li r11,32
        subfic r2,r9,16
        mtctr r11
        lvsr v13,0,r2
        addi r0,r1,64
        lvx v0,0,r9
        li r2,0
        addi r9,r1,592
L4:
        lvx v1,r2,r9
        vperm v0,v0,v1,v13
        stvx v0,r2,r0
        addi r2,r2,16
        bdz L5
        vor v0,v1,v1   /* On backarc.  */
        b L4


Generating such a copy explicitely:

      v0_init = load_vector_from_first_address
Loop:
      v0 = phi (v0_init, v0_next)
      v1 = load_vector_from_next_address
      v2 = extract (v0, v1)
      <the desired misaligned vector data now exists in v2>
      v0_next = v1
      goto Loop

did not help.


Note the difference between this pattern (where both v0 and v1 are used by
the same (extract) insn) and a standard iv pattern (which usually uses only
the pre-incremented or the post-incremented value, but not both at the same
time/insn).


How can we avoid splitting the backarc of the loop?

Ayal.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]