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Re: [PATCH] Improved target tuning in simplify-rtx.c
- From: "Joerg Beyer" <j dot beyer at web dot de>
- To: gcc at gcc dot gnu dot org, tm_gccmail at kloo dot net
- Date: Thu, 08 Jul 2004 12:25:08 +0200
- Subject: Re: [PATCH] Improved target tuning in simplify-rtx.c
- Organization: http://freemail.web.de/
you wrote:
> Ideally, you would embed a simple processor simulator in the target.c
> file. You would the call the processor model twice; once to evaluate the
> original list of insns and again to evaluate the modified list of insns
> to determine whether the optimization is profitable.
>
> Toshi
Toshi,
is looks like, that valgrind does this job already for x86 processors
with it's cachegrind tool. It sums up, a lot parameters that could be used as metric
in this case:
joerg> valgrind --tool=cachegrind /bin/ls >/dev/null
==14231== Cachegrind, an I1/D1/L2 cache profiler for x86-linux.
==14231== Copyright (C) 2002-2004, and GNU GPL'd, by Nicholas Nethercote.
==14231== Using valgrind-2.1.1, a program supervision framework for x86-linux.
==14231== Copyright (C) 2000-2004, and GNU GPL'd, by Julian Seward.
--14231-- warning: Pentium with 12 K micro-op instruction trace cache
--14231-- Simulating a 16 KB cache with 32 B lines
==14231== For more details, rerun with: -v
==14231==
==14231==
==14231== I refs: 1,689,084
==14231== I1 misses: 4,058
==14231== L2i misses: 1,534
==14231== I1 miss rate: 0.24%
==14231== L2i miss rate: 0.9%
==14231==
==14231== D refs: 1,074,618 (664,513 rd + 410,105 wr)
==14231== D1 misses: 29,134 ( 23,612 rd + 5,522 wr)
==14231== L2d misses: 4,256 ( 2,508 rd + 1,748 wr)
==14231== D1 miss rate: 2.7% ( 3.5% + 1.3% )
==14231== L2d miss rate: 0.3% ( 0.3% + 0.4% )
==14231==
==14231== L2 refs: 33,192 ( 27,670 rd + 5,522 wr)
==14231== L2 misses: 5,790 ( 4,042 rd + 1,748 wr)
==14231== L2 miss rate: 0.2% ( 0.1% + 0.4% )
hope that helps
Joerg