Re: What to do with gcc 3.4 regression on Itanium 1?

[Jim Wilson <wilson at specifixinc dot com>]

On Wed, 2004-06-02 at 12:50, H. J. Lu wrote:
> Doesn't "1_M"/"1b_M" mean that "1_ialu_addr"/"1b_ialu_addr" will be
> used for M unit only? That contradicts the comment
> ;; ??? howto describe ialu for I slot only.  We use ialu_addr for that
> which implies "ialu_addr" is for I unit.

I gave a bit of an explanation of what is going on here in PR 15598.  We
can't get both bundling and latencies exactly right, so we prefer to get
latencies right when there is an AGI stall, and bundling right
otherwise.  This can be partly confirmed by looking at the Itanium
Processor Microarchitecture Reference, which confirms that we have a
1-cycle AGI stall only when an ialu is scheduled to an I unit, and thus
the M unit should be preferred when an ialu insn produces a load/store
address.

As for the comment, it is pointing out that the 2 cycle latency applies
only to ialu insns scheduled to the I unit, but we don't have a way to
represent that.  However, we do have ialu_addr which is used for ialu
insns scheduled to the M unit, and hence by a process of elimination,
ialu insns can be assumed to be scheduled to the I unit.  This is not
exactly correct, but is an approximation.  Note that the following
define_bypass uses ialu, not ialu_addr.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com