This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: VLIW pack and DFA scheduler:Register sharing question
- From: Ayal Zaks <ZAKS at il dot ibm dot com>
- To: mike at csdn dot sign dot idv dot tw
- Cc: gcc at gcc dot gnu dot org, Dorit Naishlos <DORIT at il dot ibm dot com>
- Date: Fri, 28 May 2004 02:08:21 +0300
- Subject: Re: VLIW pack and DFA scheduler:Register sharing question
If there is a dependence of positive (non zero) latency between
two instructions, the scheduler will place them in different
"virtual" cycle. To guarantee that the HW will execute them in
different cycles, you probably need to insert noops. You may
want to use targetm.sched.dfa_bubble for that, or look at the
following noop-inserting patch of Dorit:
http://gcc.gnu.org/ml/gcc-patches/2003-10/msg01702.html
If there is a zero-latency dependence between two instructions
(e.g. an anti dependence), the scheduler may place them in
the same "virtual" cycle. You probably want to prevent that,
possibly using the targetm.sched.adjust_cost hook.
Ayal.
On Tue, 25 May 2004 mike@csdn.sign.idv.tw wrote:
...
> following situitaion?
>
> add %r1,$24
> add %r1,$28
>
> If the two asm instruction execute parallelly, the result
> of r1 could not be known.
As far as I know, no.
The DFA scheduler does not do guarantee certain restrictions. It assumes
an interlocked pipelined processor where resource contention results in
pipeline stalls, not incorrect data.
> Could DFA scheduler automatically prevent this situiation?
No.
> OR I have to add some codes to prevent this?
Yes, probably in machine-depedent reorg.
> Please help. Thanks very much.
>
>
> Mike Wu
Toshi
----- Forwarded by Dorit Naishlos/Haifa/IBM on 27/05/2004 15:05 -----
mike@bbs.sign.idv
.tw To: gcc@gcc.gnu.org
Sent by: cc:
gcc-owner@gcc.gnu Subject: VLIW pack and DFA scheduler:Register sharing question
.org
25/05/2004 13:35
Hello,
I have a question of registers shared by two vliw cpu function
units.
-----------------
| Register |
| File |
-----------------
| |
------ ------
|RISC| |RISC|
|UNIT| |UNIT|
------ ------
This two RISC units could execute instruction parallelly.
Here is my question: Could the DFA scheduler prevents the
following situitaion?
add %r1,$24
add %r1,$28
If the two asm instruction execute parallelly, the result
of r1 could not be known.
Could DFA scheduler automatically prevent this situiation?
OR I have to add some codes to prevent this?
Please help. Thanks very much.
Mike Wu