This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

Re: Why is x86_sahf_1 pattern disabled in x86_64?

From: Uros Bizjak <uros at kss-loka dot si>
To: "H. J. Lu" <hongjiu dot lu at intel dot com>
Cc: Jan Hubicka <jh at suse dot cz>, Michel Lespinasse <walken at zoy dot org>,gcc at gcc dot gnu dot org
Date: Tue, 18 May 2004 10:37:22 +0200
Subject: Re: Why is x86_sahf_1 pattern disabled in x86_64?
References: <409B6EFA.9020201@kss-loka.si> <20040507120401.GA18973@zoy.org> <20040507192814.GB3224@kam.mff.cuni.cz> <20040507200334.GA25271@lucon.org> <20040517214954.GA14867@lucon.org>

H. J. Lu wrote:

This is the current Intel's position:

Intel has no plans to support SAHF/LAHF on current processors or
future processors that include EM64T.  Intel advises against using
those instructions.  If those instructions are to be generated, they
should be under an architecture specific flag and not be included when the
compiler is expected to be generating portable code.

I guess that "x86_sahf_1" instruction should stay disabled for TARGET_64BIT. The same functionality is now implemented with test instruction if !TARGET_USE_SAHF.

Thanks,
Uros.

References:
- Why is x86_sahf_1 pattern disabled in x86_64?
  - From: Uros Bizjak
- Re: Why is x86_sahf_1 pattern disabled in x86_64?
  - From: Michel Lespinasse
- Re: Why is x86_sahf_1 pattern disabled in x86_64?
  - From: Jan Hubicka
- Re: Why is x86_sahf_1 pattern disabled in x86_64?
  - From: H. J. Lu
- Re: Why is x86_sahf_1 pattern disabled in x86_64?
  - From: H. J. Lu

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]