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Re: RFC: generic vectors and GPR/simd duality
- From: Michael Matz <matz at suse dot de>
- To: Aldy Hernandez <aldyh at redhat dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Wed, 12 May 2004 17:41:18 +0200 (CEST)
- Subject: Re: RFC: generic vectors and GPR/simd duality
- References: <20040512145800.GA31563@redhat.com>
On Wed, 12 May 2004, Aldy Hernandez wrote:
> We start with:
> (insn 14 13 15 (set (subreg:V2SI (reg:V4SI 123) 0)
> (neg:V2SI (reg:V2SI 124))) -1 (nil)
> The register allocator gives GPR #26-#30 for the V4SI mode above:
> (insn 14 13 17 0 (set (subreg:V2SI (reg:V4SI 26 26 ) 0)
> (neg:V2SI (reg:V2SI 0 0 )))
> mode_multiple from V2SI to V4SI is 2, whereas nregs_multiple is 4.
> GPR #26 can hold a V2SI in just one register, but needs 4 for a V4SI.
Hell. I believe this property should make the forming of the subreg
invalid, exactly because this makes it not something like a subword
extraction. But subregs which aren't subword extractions are only handled
correctly when one mode only needs one register (like for instance a
SI --> HI conversion on 32bit register machines) and it is the low part
(which the above isn't because this is big endian, right?).