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Re: Load insn register restrictions

From: Geert Bosch <bosch at gnat dot com>
To: Paul Brook <paul at codesourcery dot com>
Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>,Nathan Sidwell <nathan at codesourcery dot com>
Date: Sat, 17 Apr 2004 13:38:24 -0400
Subject: Re: Load insn register restrictions
References: <200404122122.24509.paul@codesourcery.com>

On Apr 12, 2004, at 16:22, Paul Brook wrote:

I'm trying to add a new doubleword load instruction to the ARM backend. It has the restriction that the index register must not be one of the destination registers. For example ldrd r0, [r2 + r3] is valid, but ldrd r0, [r2+r0] is not.
I can't figure out how to express this in the machine description.
Any suggestions?

Isn't this the '&' (earlyclobber) operand constraint?

References:
- Load insn register restrictions
  - From: Paul Brook

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