Re: How aggressive is CSE about removing redundant CC sets?

[Kazu Hirata <kazu at cs dot umass dot edu>]

Hi Ian,

> As far as CSE is concerned, setting a condition code register is an
> expression like any other.

That's what I thought.

> I do note that your RTL here shows only hard registers.  Remember that
> CSE is only run relatively early in the set of passes.  I'm not sure
> whether the reload_cse_regs() pass will pick this up--I would expect
> it to, but I haven't looked closely at the code recently.

I should have posted the rtl right before CSE, which is:

(parallel [(set (reg:SI 19)
                (reg:SI 20))
	   (set (reg:CC 12 cc)
                (compare:CC (reg:SI 20)
			    (const_int 0)))])

(set (reg:CC 12 cc)
     (compare:CC (reg:SI 19)
		 (const_int 0)))

The compare expressions aren't identical, but CSE should notice and
take advantage of the equivalence of (reg:SI 19) and (reg:SI 20).
I'll try to look into this.  (Interestingly, the redundant compare
insn went away when I flipped the order of the two sets in the first
insn.)

Kazu Hirata