This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: m68k bootstrapping broken


Bernardo Innocenti <bernie@develer.com> writes:

> Andreas Schwab wrote:
>> Bernardo Innocenti <bernie@develer.com> writes:
>> 
>>>Another thing.  I'm playing with libffi to see if I can get it to work
>>>on plain 68000.   Do you know a simple instruction sequence to replace
>>>this bit-field operation?
>>>
>>>   bfins   %d0,(%a1){#0,%d2}
>>>
>>>
>>>I was thinking of something like this (in pseudo-C):
>>>
>>>   mask = (1 << (d2 & 0x1f)) - 1;
>>>   *a1 = (*a2 & ~mask) | (d0 & mask);
>> The mask is wrong. The bitfield insns number the bits from MSB to LSB,
>> not
>> the other way round, as the single bit insns do.  Also, a width of 0 is
>> replaced by 32.
>   ^^^^^^^^^^^^^^
>
> This does only happen for immediate modes

No, also for non-immediate.  A bitfield can never be empty.

    Width field
      Specifies the field width, depending on Dw.
        If Dw = 0, the width field is an immediate operand; an operand
          value in the range 1 - 31 specifies a field width of 1 - 31, and
          a value of zero specifies a width of 32.
        If Dw = 1, the width field specifies a data register that contains
          the width. The value is modulo 32; values of 1 - 31 specify
          field widths of 1 - 31, and a value of zero specifies a width of
          32.

Andreas.

-- 
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux AG, Maxfeldstraße 5, 90409 Nürnberg, Germany
Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]