This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: latency in define_insn_reservation


ml@bitbash.net wrote:
If instr I is issued cycle = t and the results are usable in cylce t+1, should the latency in define_insn_reservation be 1 or 0?

The latency should be 1. Try looking at existing dfa scheduler descriptions. I doubt that you will find any that use a latency of zero, but there are lots that use a latency of 1 for simple instructions that you would expect to have single cycle latency.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com



Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]