This is the FAST version. ;; Function Part_Traverse try_optimize_cfg iteration 1 try_optimize_cfg iteration 1 Removing jump 39. Removing jump 699. Removing jump 696. Removing jump 394. Removing jump 715. try_optimize_cfg iteration 2 STC - round 1 Getting bb 0 Basic block 0 was visited in trace 0 Possible start of this round: 2 (key: -5833) Basic block 1 was visited in trace 0 Block 2 can't be copied because its size = 15. Basic block 2 was visited in trace 0 Possible start of next round: 4 (key: -1750) Basic block 3 was visited in trace 0 Block 32 can't be copied because its size = 13. Basic block 32 was visited in trace 0 Block 35 can't be copied because its size = 14. Possible start of next round: 33 (key: -1743) Basic block 35 was visited in trace 0 STC - round 2 Getting bb 4 Basic block 4 was visited in trace 1 Possible start of next round: 5 (key: -875) Possible start of next round: 9 (key: -1750) Changing key for bb 5 from -875 to -1088375. Changing key for bb 9 from -1750 to -1089250. Getting bb 33 Basic block 33 was visited in trace 2 Possible start of this round: 34 (key: -1750) Changing key for bb 34 from -1750 to -1176050. Getting bb 34 Basic block 34 was visited in trace 3 STC - round 3 Getting bb 9 Basic block 9 was visited in trace 4 Possible start of this round: 16 (key: -1750) Basic block 10 was visited in trace 4 Possible start of next round: 14 (key: -263) Basic block 11 was visited in trace 4 Possible start of this round: 13 (key: -306) Basic block 12 was visited in trace 4 Possible start of this round: 15 (key: -875) Changing key for bb 15 from -875 to -1031475. Getting bb 5 Basic block 5 was visited in trace 5 Possible start of next round: 7 (key: -569) Basic block 6 was visited in trace 5 Block 7 can't be copied because its size = 52. Basic block 7 was visited in trace 5 Possible start of next round: 8 (key: -171) Changing key for bb 8 from -171 to -1017271. Getting bb 15 Basic block 15 was visited in trace 6 Block 16 can't be copied because its size = 10. Basic block 16 was visited in trace 6 Basic block 17 was visited in trace 6 Block 18 can't be copied because its size = 40. Basic block 18 was visited in trace 6 Block 21 can't be copied because its size = 8. Possible start of this round: 19 (key: -3000) Basic block 21 was visited in trace 6 Possible start of this round: 28 (key: -9527) Possible start of this round: 22 (key: -3000) Changing key for bb 28 from -9527 to -1709527. Changing key for bb 22 from -3000 to -1303000. Getting bb 28 Basic block 28 was visited in trace 7 Block 31 can't be copied because its size = 25. Basic block 31 was visited in trace 7 Getting bb 22 Basic block 22 was visited in trace 8 Basic block 23 was visited in trace 8 Possible start of this round: 25 (key: -900) Basic block 24 was visited in trace 8 Block 25 can't be copied because its size = 13. Basic block 25 was visited in trace 8 Basic block 26 was visited in trace 8 Possible start of next round: 29 (key: -22) Basic block 27 was visited in trace 8 Getting bb 19 Basic block 19 was visited in trace 9 Basic block 20 was visited in trace 9 Getting bb 13 Basic block 13 was visited in trace 10 STC - round 4 Getting bb 8 Basic block 8 was visited in trace 11 Getting bb 14 Basic block 14 was visited in trace 12 Getting bb 29 Basic block 29 was visited in trace 13 Basic block 30 was visited in trace 13 Trace 1 (round 1): 0 [5833] 1 [2917] 2 [5833] 3 [4083] 32 [5811] 35 [5833] Trace 2 (round 2): 4 [1750] Trace 3 (round 2): 33 [1743] Trace 4 (round 2): 34 [1750] Trace 5 (round 3): 9 [1750] 10 [875] 11 [613] 12 [306] Trace 6 (round 3): 5 [875] 6 [613] 7 [569] Trace 7 (round 3): 15 [875] 16 [1750] 17 [1120] 18 [10000] 21 [10000] Trace 8 (round 3): 28 [9527] 31 [9977] Trace 9 (round 3): 22 [3000] 23 [900] 24 [450] 25 [900] 26 [450] 27 [427] Trace 10 (round 3): 19 [3000] 20 [900] Trace 11 (round 3): 13 [306] Trace 12 (round 4): 8 [171] Trace 13 (round 4): 14 [263] Trace 14 (round 4): 29 [22] 30 [7] Connection: 4 9 Connection: 12 15 Connection: 21 28 Connection: 31 18 19 Edge 31->18 redirected to 36 Duplicated bb 18 (created bb 36) Connection: 20 21 22 Fallthru edge 20->37 redirected to 37 Duplicated bb 21 (created bb 37) Connection: 33 34 Connection: 34 35 exit Fallthru edge 34->38 redirected to 38 Duplicated bb 35 (created bb 38) Connection: 7 8 Connection: 30 34 Fallthru edge 30->39 redirected to 39 Duplicated bb 34 (created bb 39) Final order: 0 1 2 3 32 35 4 9 10 11 12 15 16 17 18 21 28 31 36 19 20 37 22 23 24 25 26 27 33 34 38 5 6 7 8 13 14 29 30 39 191 registers. 40 basic blocks, 63 edges. Basic block 0: first insn 520, last 19, prev -1, next 1, loop_depth 0, count 0, freq 5833, maybe hot. Predecessors: ENTRY [100.0%] (fallthru) Successors: 1 [50.0%] (fallthru,can_fallthru) 2 [50.0%] (can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 1: first insn 523, last 29, prev 0, next 2, loop_depth 0, count 0, freq 2917, maybe hot. Predecessors: 0 [50.0%] (fallthru,can_fallthru) Successors: 2 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 2: first insn 30, last 34, prev 1, next 3, loop_depth 0, count 0, freq 5833, maybe hot. Predecessors: 1 [100.0%] (fallthru,can_fallthru) 0 [50.0%] (can_fallthru) Successors: 3 [70.0%] (fallthru,can_fallthru) 4 [30.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 3: first insn 526, last 38, prev 2, next 4, loop_depth 0, count 0, freq 4083, maybe hot. Predecessors: 2 [70.0%] (fallthru,can_fallthru) Successors: 32 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 4: first insn 41, last 67, prev 3, next 5, loop_depth 0, count 0, freq 1750, maybe hot. Predecessors: 2 [30.0%] (can_fallthru) Successors: 5 [50.0%] (fallthru,can_fallthru) 9 [50.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 5: first insn 529, last 74, prev 4, next 6, loop_depth 0, count 0, freq 875, maybe hot. Predecessors: 4 [50.0%] (fallthru,can_fallthru) Successors: 6 [70.0%] (fallthru,can_fallthru) 7 [30.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 6: first insn 531, last 83, prev 5, next 7, loop_depth 0, count 0, freq 613, maybe hot. Predecessors: 5 [70.0%] (fallthru,can_fallthru) Successors: 7 [50.0%] (fallthru,can_fallthru) 9 [50.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 7: first insn 86, last 113, prev 6, next 8, loop_depth 0, count 0, freq 569, maybe hot. Predecessors: 6 [50.0%] (fallthru,can_fallthru) 5 [30.0%] (can_fallthru) Successors: 8 [30.0%] (fallthru,can_fallthru) 9 [70.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 8: first insn 535, last 126, prev 7, next 9, loop_depth 0, count 0, freq 171, maybe hot. Predecessors: 7 [30.0%] (fallthru,can_fallthru) Successors: 9 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 9: first insn 130, last 134, prev 8, next 10, loop_depth 0, count 0, freq 1750, maybe hot. Predecessors: 8 [100.0%] (fallthru,can_fallthru) 7 [70.0%] (can_fallthru) 6 [50.0%] (can_fallthru) 4 [50.0%] (can_fallthru) Successors: 10 [50.0%] (fallthru,can_fallthru) 16 [50.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 10: first insn 540, last 149, prev 9, next 11, loop_depth 0, count 0, freq 875, maybe hot. Predecessors: 9 [50.0%] (fallthru,can_fallthru) Successors: 11 [70.0%] (fallthru,can_fallthru) 14 [30.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 11: first insn 542, last 159, prev 10, next 12, loop_depth 0, count 0, freq 613, maybe hot. Predecessors: 10 [70.0%] (fallthru,can_fallthru) Successors: 12 [50.0%] (fallthru,can_fallthru) 13 [50.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 12: first insn 544, last 176, prev 11, next 13, loop_depth 0, count 0, freq 306, maybe hot. Predecessors: 11 [50.0%] (fallthru,can_fallthru) Successors: 15 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 13: first insn 182, last 196, prev 12, next 14, loop_depth 0, count 0, freq 306, maybe hot. Predecessors: 11 [50.0%] (can_fallthru) Successors: 15 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 14: first insn 202, last 214, prev 13, next 15, loop_depth 0, count 0, freq 263, maybe hot. Predecessors: 10 [30.0%] (can_fallthru) Successors: 15 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 15: first insn 695, last 216, prev 14, next 16, loop_depth 0, count 0, freq 875, maybe hot. Predecessors: 12 [100.0%] (fallthru,can_fallthru) 13 [100.0%] (fallthru,can_fallthru) 14 [100.0%] (fallthru,can_fallthru) Successors: 16 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 16: first insn 218, last 596, prev 15, next 17, loop_depth 0, count 0, freq 1750, maybe hot. Predecessors: 15 [100.0%] (fallthru,can_fallthru) 9 [50.0%] (can_fallthru) Successors: 17 [64.0%] (fallthru,can_fallthru) 32 [36.0%] (can_fallthru) Registers live at start: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 4 [si] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 17: first insn 608, last 719, prev 16, next 18, loop_depth 0, count 0, freq 1120, maybe hot. Predecessors: 16 [64.0%] (fallthru,can_fallthru) Successors: 18 [100.0%] (fallthru,can_fallthru) Registers live at start: 4 [si] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 18: first insn 222, last 243, prev 17, next 19, loop_depth 1, count 0, freq 1120, maybe hot. Predecessors: 17 [100.0%] (fallthru,can_fallthru) Successors: 19 [30.0%] (fallthru,can_fallthru) 21 [70.0%] (can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 19: first insn 551, last 270, prev 18, next 20, loop_depth 1, count 0, freq 3000, maybe hot. Predecessors: 36 [30.0%] (fallthru,can_fallthru) 18 [30.0%] (fallthru,can_fallthru) Successors: 20 [30.0%] (fallthru,can_fallthru) 21 [70.0%] (can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 20: first insn 553, last 283, prev 19, next 21, loop_depth 1, count 0, freq 900, maybe hot. Predecessors: 19 [30.0%] (fallthru,can_fallthru) Successors: 37 [100.0%] (fallthru,can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 21: first insn 286, last 289, prev 20, next 22, loop_depth 1, count 0, freq 9100, maybe hot. Predecessors: 36 [70.0%] (can_fallthru) 19 [70.0%] (can_fallthru) 18 [70.0%] (can_fallthru) Successors: 28 [70.0%] (can_fallthru) 22 [30.0%] (fallthru,can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 22: first insn 558, last 316, prev 21, next 23, loop_depth 1, count 0, freq 3000, maybe hot. Predecessors: 37 [30.0%] (fallthru,can_fallthru) 21 [30.0%] (fallthru,can_fallthru) Successors: 28 [70.0%] (can_fallthru) 23 [30.0%] (fallthru,can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 23: first insn 561, last 338, prev 22, next 24, loop_depth 1, count 0, freq 900, maybe hot. Predecessors: 22 [30.0%] (fallthru,can_fallthru) Successors: 24 [50.0%] (fallthru,can_fallthru) 25 [50.0%] (can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 24: first insn 563, last 344, prev 23, next 25, loop_depth 1, count 0, freq 450, maybe hot. Predecessors: 23 [50.0%] (fallthru,can_fallthru) Successors: 25 [100.0%] (fallthru,can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 25: first insn 345, last 349, prev 24, next 26, loop_depth 1, count 0, freq 900, maybe hot. Predecessors: 24 [100.0%] (fallthru,can_fallthru) 23 [50.0%] (can_fallthru) Successors: 26 [50.0%] (fallthru,can_fallthru) 31 [50.0%] (can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 26: first insn 566, last 357, prev 25, next 27, loop_depth 1, count 0, freq 450, maybe hot. Predecessors: 25 [50.0%] (fallthru,can_fallthru) Successors: 27 [95.0%] (fallthru,can_fallthru) 29 [5.0%] (can_fallthru,loop_exit) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 27: first insn 568, last 390, prev 26, next 28, loop_depth 1, count 0, freq 427, maybe hot. Predecessors: 26 [95.0%] (fallthru,can_fallthru) Successors: 28 [100.0%] (fallthru,can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 28: first insn 703, last 393, prev 27, next 29, loop_depth 1, count 0, freq 9527, maybe hot. Predecessors: 37 [70.0%] (can_fallthru) 22 [70.0%] (can_fallthru) 21 [70.0%] (can_fallthru) 27 [100.0%] (fallthru,can_fallthru) Successors: 31 [100.0%] (fallthru,can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 29: first insn 396, last 434, prev 28, next 30, loop_depth 0, count 0, freq 22, maybe hot. Predecessors: 26 [5.0%] (can_fallthru,loop_exit) Successors: 30 [30.0%] (fallthru,can_fallthru) 35 [70.0%] (can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 30: first insn 572, last 452, prev 29, next 31, loop_depth 0, count 0, freq 7. Predecessors: 29 [30.0%] (fallthru,can_fallthru) Successors: 39 [100.0%] (fallthru,can_fallthru) Registers live at start: 1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 31: first insn 466, last 477, prev 30, next 32, loop_depth 1, count 0, freq 9977, maybe hot. Predecessors: 28 [100.0%] (fallthru,can_fallthru) 25 [50.0%] (can_fallthru) Successors: 32 [11.0%] (fallthru,can_fallthru,loop_exit) 36 [89.0%] (dfs_back,can_fallthru) Registers live at start: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 32: first insn 481, last 484, prev 31, next 33, loop_depth 0, count 0, freq 5811, maybe hot. Predecessors: 31 [11.0%] (fallthru,can_fallthru,loop_exit) 16 [36.0%] (can_fallthru) 3 [100.0%] (fallthru,can_fallthru) Successors: 33 [30.0%] (fallthru,can_fallthru) 35 [70.0%] (can_fallthru) Registers live at start: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 33: first insn 584, last 502, prev 32, next 34, loop_depth 0, count 0, freq 1743, maybe hot. Predecessors: 32 [30.0%] (fallthru,can_fallthru) Successors: 34 [100.0%] (fallthru,can_fallthru) Registers live at start: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 34: first insn 714, last 503, prev 33, next 35, loop_depth 0, count 0, freq 1743, maybe hot. Predecessors: 33 [100.0%] (fallthru,can_fallthru) Successors: 38 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 35: first insn 508, last 691, prev 34, next 36, loop_depth 0, count 0, freq 4083, maybe hot. Predecessors: 29 [70.0%] (can_fallthru) 32 [70.0%] (can_fallthru) Successors: EXIT [100.0%] Registers live at start: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 36: first insn 740, last 737, prev 35, next 37, loop_depth 1, count 0, freq 8880, maybe hot. Predecessors: 31 [89.0%] (dfs_back,can_fallthru) Successors: 21 [70.0%] (can_fallthru) 19 [30.0%] (fallthru,can_fallthru) Registers live at start: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 37: first insn 744, last 743, prev 36, next 38, loop_depth 1, count 0, freq 900, maybe hot. Predecessors: 20 [100.0%] (fallthru,can_fallthru) Successors: 22 [30.0%] (fallthru,can_fallthru) 28 [70.0%] (can_fallthru) Registers live at start: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 38: first insn 754, last 753, prev 37, next 39, loop_depth 0, count 0, freq 1750, maybe hot. Predecessors: 39 [100.0%] (fallthru,can_fallthru) 34 [100.0%] (fallthru,can_fallthru) Successors: EXIT [100.0%] Registers live at start: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Basic block 39: first insn 759, last 758, prev 38, next -2, loop_depth 0, count 0, freq 7. Predecessors: 30 [100.0%] (fallthru,can_fallthru) Successors: 38 [100.0%] (fallthru,can_fallthru) Registers live at start: 6 [bp] 7 [sp] 16 [argp] 20 [frame] Registers live at end: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] Emitting label for block 33 Emitting label for block 5 Emitting label for block 19 Emitting label for block 22 Reordered sequence: 0 bb 0 [5833] 1 bb 1 [2917] 2 bb 2 [5833] 3 bb 3 [4083] 4 bb 32 [5811] 5 bb 35 [4083] 6 bb 4 [1750] 7 bb 9 [1750] 8 bb 10 [875] 9 bb 11 [613] 10 bb 12 [306] 11 bb 15 [875] 12 bb 16 [1750] 13 bb 17 [1120] 14 bb 18 [1120] 15 bb 21 [9100] 16 bb 28 [9527] 17 bb 31 [9977] 18 duplicate of 18 [8880] 19 bb 19 [3000] 20 bb 20 [900] 21 duplicate of 21 [900] 22 bb 22 [3000] 23 bb 23 [900] 24 bb 24 [450] 25 bb 25 [900] 26 bb 26 [450] 27 bb 27 [427] 28 bb 33 [1743] 29 bb 34 [1743] 30 duplicate of 35 [1750] 31 bb 5 [875] 32 bb 6 [613] 33 bb 7 [569] 34 bb 8 [171] 35 bb 13 [306] 36 bb 14 [263] 37 bb 29 [22] 38 bb 30 [7] 39 duplicate of 34 [7] try_optimize_cfg iteration 1 Merged 13 and 14 without moving. Deleted label in block 18. Merged 20 and 21 without moving. Merged 28 and 29 without moving. Merged 38 and 39 without moving. try_optimize_cfg iteration 2 (note:HI 2 0 520 NOTE_INSN_DELETED) ;; Start of basic block 0, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 520 2 678 0 [bb 0] NOTE_INSN_BASIC_BLOCK) (insn/f 678 520 679 0 (set (mem:SI (pre_dec:SI (reg/f:SI %esp)) [0 S4 A8]) (reg/f:SI %ebp)) 32 {*pushsi2} (nil) (nil)) (insn/f 679 678 680 0 (set (reg/f:SI %ebp) (reg/f:SI %esp)) 38 {*movsi_1} (nil) (nil)) (insn/f 680 679 681 0 (set (mem:SI (pre_dec:SI (reg/f:SI %esp)) [0 S4 A8]) (reg:SI %edi)) 32 {*pushsi2} (nil) (expr_list:REG_DEAD (reg:SI %edi) (nil))) (insn/f 681 680 682 0 (set (mem:SI (pre_dec:SI (reg/f:SI %esp)) [0 S4 A8]) (reg:SI %esi)) 32 {*pushsi2} (nil) (expr_list:REG_DEAD (reg:SI %esi) (nil))) (insn/f 682 681 683 0 (set (mem:SI (pre_dec:SI (reg/f:SI %esp)) [0 S4 A8]) (reg:SI %ebx)) 32 {*pushsi2} (nil) (expr_list:REG_DEAD (reg:SI %ebx) (nil))) (insn/f 683 682 684 0 (parallel [ (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int -60 [0xffffffc4]))) (clobber (reg:CC %eflags)) (clobber (mem:BLK (scratch) [0 A8])) ]) 515 {*pro_epilogue_adjust_stack_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (note 684 683 3 0 NOTE_INSN_PROLOGUE_END) (note:HI 3 684 4 0 NOTE_INSN_DELETED) (note:HI 4 3 5 0 NOTE_INSN_DELETED) (note:HI 5 4 6 0 NOTE_INSN_DELETED) (note:HI 6 5 7 0 NOTE_INSN_DELETED) (note:HI 7 6 8 0 NOTE_INSN_DELETED) (note:HI 8 7 674 0 NOTE_INSN_FUNCTION_BEG) (insn 674 8 675 0 (set (reg:SI %eax [orig:64 NullToken.256 ] [64]) (mem/s:SI (symbol_ref:SI ("NullToken") [flags 0x40] ) [12 NullToken+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 675 674 676 0 (set (reg:SI %edx [ NullToken.256+4 ]) (mem/s:SI (const:SI (plus:SI (symbol_ref:SI ("NullToken") [flags 0x40] ) (const_int 4 [0x4]))) [12 NullToken+4 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 676 675 677 0 (set (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -32 [0xffffffe0])) [12 S4 A8]) (reg:SI %eax [orig:64 NullToken.256 ] [64])) 38 {*movsi_1} (insn_list 674 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:64 NullToken.256 ] [64]) (nil))) (insn 677 676 603 0 (set (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -28 [0xffffffe4])) [12 S4 A8]) (reg:SI %edx [ NullToken.256+4 ])) 38 {*movsi_1} (insn_list 675 (nil)) (expr_list:REG_DEAD (reg:SI %edx [ NullToken.256+4 ]) (nil))) (insn:HI 603 677 725 0 (set (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) [23 S4 A8]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 725 603 726 0 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 726 725 19 0 (set (reg:CCNO %eflags) (compare:CCNO (reg:SI %eax) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (jump_insn:HI 19 726 523 0 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 30) (pc))) 366 {*jcc_1} (insn_list 18 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 0, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 1, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 523 19 629 1 [bb 1] NOTE_INSN_BASIC_BLOCK) (insn 629 523 24 1 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 24 629 25 1 (set (reg:SI %eax [orig:65 T.257 ] [65]) (mem/s:SI (reg:SI %edx) [3 .Handle+0 S4 A32])) 38 {*movsi_1} (insn_list 629 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (expr_list:REG_EQUIV (mem/s:SI (reg:SI %edx) [3 .Handle+0 S4 A32]) (nil)))) (insn:HI 25 24 27 1 (set (mem/f:SI (symbol_ref:SI ("*SeedHandle.7") [flags 0x2] ) [3 SeedHandle+0 S4 A32]) (reg:SI %eax [orig:65 T.257 ] [65])) 38 {*movsi_1} (insn_list 24 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:65 T.257 ] [65]) (nil))) (insn:HI 27 25 29 1 (set (mem/f:SI (symbol_ref:SI ("DrawObjs") [flags 0x40] ) [3 DrawObjs+0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 29 27 30 1 (set (mem/f:SI (symbol_ref:SI ("Points") [flags 0x40] ) [3 Points+0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) ;; End of basic block 1, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 2, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 30 29 524 2 248 "" [1 uses]) (note:HI 524 30 32 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note:HI 32 524 630 2 NOTE_INSN_DELETED) (insn 630 32 33 2 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 33 630 34 2 (set (reg:CC %eflags) (compare:CC (reg:SI %ecx) (mem/f:SI (symbol_ref:SI ("Traverse_Limit") [flags 0x40] ) [14 Traverse_Limit+0 S4 A32]))) 2 {*cmpsi_1_insn} (insn_list 630 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (jump_insn:HI 34 33 526 2 (set (pc) (if_then_else (ltu (reg:CC %eflags) (const_int 0 [0x0])) (label_ref 41) (pc))) 366 {*jcc_1} (insn_list 33 (nil)) (expr_list:REG_DEAD (reg:CC %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 2, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 3, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 526 34 631 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (insn 631 526 38 3 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 38 631 481 3 (set (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 631 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) ;; End of basic block 3, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 4, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 481 38 581 4 251 "" [2 uses]) (note:HI 581 481 488 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn:HI 488 581 483 4 (set (reg:SI %eax [orig:105 iftmp.297 ] [105]) (const_int 1 [0x1])) 38 {*movsi_1} (nil) (nil)) (insn:HI 483 488 484 4 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (nil)) (jump_insn:HI 484 483 508 4 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 760) (pc))) 366 {*jcc_1} (insn_list 483 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 4, registers live: 0 [ax] 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 5, registers live: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 508 484 585 5 292 "" [1 uses]) (note:HI 585 508 509 5 [bb 5] NOTE_INSN_BASIC_BLOCK) (insn:HI 509 585 513 5 (set (mem/f:SI (symbol_ref:SI ("Test") [flags 0x40] ) [2 Test+0 S4 A32]) (reg:SI %eax [orig:105 iftmp.297 ] [105])) 38 {*movsi_1} (nil) (nil)) (note:HI 513 509 519 5 NOTE_INSN_FUNCTION_END) (insn 519 513 685 5 (use (reg/i:SI %eax [ ])) -1 (nil) (nil)) (note 685 519 686 5 NOTE_INSN_EPILOGUE_BEG) (insn 686 685 687 5 (parallel [ (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 60 [0x3c]))) (clobber (reg:CC %eflags)) (clobber (mem:BLK (scratch) [0 A8])) ]) 515 {*pro_epilogue_adjust_stack_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn 687 686 688 5 (parallel [ (set (reg:SI %ebx) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (insn_list 686 (nil)) (nil)) (insn 688 687 689 5 (parallel [ (set (reg:SI %esi) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (insn_list 687 (nil)) (nil)) (insn 689 688 690 5 (parallel [ (set (reg:SI %edi) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (insn_list 688 (nil)) (nil)) (insn 690 689 691 5 (parallel [ (set (reg/f:SI %ebp) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (insn_list 689 (nil)) (nil)) (jump_insn 691 690 692 5 (return) 388 {return_internal} (nil) (nil)) ;; End of basic block 5, registers live: 0 [ax] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 692 691 41) ;; Start of basic block 6, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 41 692 527 6 249 "" [1 uses]) (note:HI 527 41 43 6 [bb 6] NOTE_INSN_BASIC_BLOCK) (note:HI 43 527 44 6 NOTE_INSN_DELETED) (note:HI 44 43 45 6 NOTE_INSN_DELETED) (insn:HI 45 44 47 6 (parallel [ (set (mem/f:SI (symbol_ref:SI ("*Traverses.8") [flags 0x2] ) [3 Traverses+0 S4 A32]) (plus:SI (mem/f:SI (symbol_ref:SI ("*Traverses.8") [flags 0x2] ) [3 Traverses+0 S4 A32]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn:HI 47 45 58 6 (set (reg/f:SI %eax [orig:69 PartObj.261 ] [69]) (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec]))) 150 {*lea_1} (nil) (expr_list:REG_EQUIV (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) (nil))) (insn:HI 58 47 632 6 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (reg/f:SI %eax [orig:69 PartObj.261 ] [69])) 38 {*movsi_1} (insn_list 47 (nil)) (expr_list:REG_DEAD (reg/f:SI %eax [orig:69 PartObj.261 ] [69]) (nil))) (insn 632 58 59 6 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 59 632 60 6 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 632 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 60 59 61 6 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 61 60 633 6 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 633 61 62 6 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 62 633 63 6 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 633 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 63 62 66 6 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Object_GetImage") [flags 0x41] ) [0 S1 A8]) (const_int 20 [0x14]))) 531 {*call_value_0} (nil) (nil) (nil)) (insn:HI 66 63 67 6 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %eax [orig:70 T.262 ] [70]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 63 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:70 T.262 ] [70]) (nil))) (jump_insn:HI 67 66 130 6 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 761) (pc))) 366 {*jcc_1} (insn_list 66 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 6, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 7, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 130 67 538 7 258 "" [3 uses]) (note:HI 538 130 637 7 [bb 7] NOTE_INSN_BASIC_BLOCK) (insn 637 538 131 7 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 131 637 133 7 (set (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 637 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (insn:HI 133 131 134 7 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 131 (nil)) (nil)) (jump_insn:HI 134 133 540 7 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 218) (pc))) 366 {*jcc_1} (insn_list 133 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 7, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 8, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 540 134 139 8 [bb 8] NOTE_INSN_BASIC_BLOCK) (insn:HI 139 540 140 8 (set (reg:SI %ecx [orig:131 Traverses ] [131]) (mem/f:SI (symbol_ref:SI ("*Traverses.8") [flags 0x2] ) [3 Traverses+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/f:SI (symbol_ref:SI ("*Traverses.8") [flags 0x2] ) [3 Traverses+0 S4 A32]) (nil))) (insn:HI 140 139 638 8 (set (reg:SI %edx [133]) (const_int -858993459 [0xcccccccd])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (const_int -858993459 [0xcccccccd]) (nil))) (insn 638 140 141 8 (set (reg:SI %eax) (reg:SI %ecx [orig:131 Traverses ] [131])) 38 {*movsi_1} (insn_list 139 (nil)) (nil)) (insn:HI 141 638 142 8 (parallel [ (set (reg:SI %edx [132]) (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (reg:SI %eax)) (zero_extend:DI (reg:SI %edx [133]))) (const_int 32 [0x20])))) (clobber (reg:SI %eax)) (clobber (reg:CC %eflags)) ]) 195 {*umulsi3_highpart_insn} (insn_list 140 (insn_list 638 (nil))) (expr_list:REG_DEAD (reg:SI %eax) (expr_list:REG_UNUSED (reg:SI %eax) (expr_list:REG_UNUSED (reg:CC %eflags) (expr_list:REG_EQUAL (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (reg:SI %ecx [orig:131 Traverses ] [131])) (const_double -858993459 [0xcccccccd] 0 [0x0] 0 [0x0] 0 [0x0] 0 [0x0] 0 [0x0])) (const_int 32 [0x20]))) (nil)))))) (insn:HI 142 141 144 8 (parallel [ (set (reg:SI %edx [132]) (lshiftrt:SI (reg:SI %edx [132]) (const_int 3 [0x3]))) (clobber (reg:CC %eflags)) ]) 333 {*lshrsi3_1} (insn_list 141 (nil)) (expr_list:REG_UNUSED (reg:CC %eflags) (expr_list:REG_EQUAL (udiv:SI (reg:SI %ecx [orig:131 Traverses ] [131]) (const_int 10 [0xa])) (nil)))) (note:HI 144 142 145 8 NOTE_INSN_DELETED) (insn:HI 145 144 146 8 (set (reg:SI %edx [136]) (plus:SI (mult:SI (reg:SI %edx [132]) (const_int 4 [0x4])) (reg:SI %edx [132]))) 150 {*lea_1} (insn_list 142 (nil)) (nil)) (insn:HI 146 145 147 8 (parallel [ (set (reg:SI %edx [137]) (ashift:SI (reg:SI %edx [136]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 304 {*ashlsi3_1} (insn_list 145 (nil)) (expr_list:REG_UNUSED (reg:CC %eflags) (expr_list:REG_EQUAL (mult:SI (reg:SI 130) (const_int 10 [0xa])) (nil)))) (note:HI 147 146 148 8 NOTE_INSN_DELETED) (insn:HI 148 147 149 8 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:131 Traverses ] [131]) (reg:SI %edx [137]))) 2 {*cmpsi_1_insn} (insn_list 146 (nil)) (expr_list:REG_DEAD (reg:SI %ecx [orig:131 Traverses ] [131]) (expr_list:REG_DEAD (reg:SI %edx [137]) (nil)))) (jump_insn:HI 149 148 542 8 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 202) (pc))) 366 {*jcc_1} (insn_list 148 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 8, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 9, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 542 149 154 9 [bb 9] NOTE_INSN_BASIC_BLOCK) (insn:HI 154 542 670 9 (set (reg:SI %edx [orig:79 CallCount.271 ] [79]) (mem/f:SI (symbol_ref:SI ("*CallCount.9") [flags 0x2] ) [3 CallCount+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 670 154 156 9 (set (reg:SI %eax [139]) (plus:SI (reg:SI %edx [orig:79 CallCount.271 ] [79]) (const_int 1 [0x1]))) 150 {*lea_1} (insn_list 154 (nil)) (nil)) (insn:HI 156 670 157 9 (set (mem/f:SI (symbol_ref:SI ("*CallCount.9") [flags 0x2] ) [3 CallCount+0 S4 A32]) (reg:SI %eax [139])) 38 {*movsi_1} (insn_list 670 (nil)) (expr_list:REG_DEAD (reg:SI %eax [139]) (nil))) (note:HI 157 156 721 9 NOTE_INSN_DELETED) (insn 721 157 159 9 (parallel [ (set (reg:CCNO %eflags) (compare:CCNO (and:QI (reg:QI %dl [orig:79 CallCount.271 ] [79]) (const_int 1 [0x1])) (const_int 0 [0x0]))) (set (reg:QI %dl [orig:79 CallCount.271 ] [79]) (and:QI (reg:QI %dl [orig:79 CallCount.271 ] [79]) (const_int 1 [0x1]))) ]) 219 {*andqi_2} (nil) (expr_list:REG_UNUSED (reg:QI %dl [orig:79 CallCount.271 ] [79]) (nil))) (jump_insn:HI 159 721 544 9 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 182) (pc))) 366 {*jcc_1} (insn_list 671 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 9, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 10, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 544 159 639 10 [bb 10] NOTE_INSN_BASIC_BLOCK) (insn 639 544 172 10 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 172 639 173 10 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 639 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 173 172 174 10 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 174 173 640 10 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 640 174 175 10 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 175 640 176 10 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 640 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 176 175 695 10 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("BMT_Validate") [flags 0x41] ) [0 S1 A8]) (const_int 16 [0x10]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) ;; End of basic block 10, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 11, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 695 176 693 11 294 "" [2 uses]) (note 693 695 646 11 [bb 11] NOTE_INSN_BASIC_BLOCK) (insn 646 693 216 11 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 216 646 218 11 (set (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 646 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) ;; End of basic block 11, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 12, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 218 216 548 12 265 "" [1 uses]) (note:HI 548 218 720 12 [bb 12] NOTE_INSN_BASIC_BLOCK) (insn 720 548 590 12 (parallel [ (set (reg/v:SI %esi [orig:111 j ] [111]) (const_int 0 [0x0])) (clobber (reg:CC %eflags)) ]) 36 {*movsi_xor} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (note:HI 590 720 591 12 NOTE_INSN_DELETED) (note:HI 591 590 594 12 NOTE_INSN_DELETED) (note:HI 594 591 595 12 NOTE_INSN_DELETED) (insn:HI 595 594 596 12 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (nil)) (jump_insn:HI 596 595 608 12 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 481) (pc))) 366 {*jcc_1} (insn_list 595 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3600 [0xe10]) (nil)))) ;; End of basic block 12, registers live: 2 [cx] 4 [si] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 13, registers live: 4 [si] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 608 596 607 13 [bb 13] NOTE_INSN_BASIC_BLOCK) (note:HI 607 608 719 13 NOTE_INSN_DELETED) (insn 719 607 588 13 (parallel [ (set (reg:SI %edi [187]) (const_int 0 [0x0])) (clobber (reg:CC %eflags)) ]) 36 {*movsi_xor} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (note:HI 588 719 224 13 NOTE_INSN_LOOP_BEG) (note:HI 224 588 225 13 NOTE_INSN_DELETED) (note:HI 225 224 226 13 NOTE_INSN_DELETED) (insn:HI 226 225 228 13 (parallel [ (set (mem/f:SI (symbol_ref:SI ("PartCount") [flags 0x40] ) [14 PartCount+0 S4 A32]) (plus:SI (mem/f:SI (symbol_ref:SI ("PartCount") [flags 0x40] ) [14 PartCount+0 S4 A32]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (note:HI 228 226 647 13 NOTE_INSN_DELETED) (insn 647 228 233 13 (set (reg:SI %eax [152]) (reg:SI %edi [187])) 38 {*movsi_1} (nil) (nil)) (insn:HI 233 647 235 13 (parallel [ (set (reg:SI %eax [152]) (plus:SI (reg:SI %eax [152]) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) [23 S4 A32]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (insn_list 647 (nil)) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn:HI 235 233 648 13 (set (reg/v:SI %ebx [orig:110 ToPart ] [110]) (mem/s:SI (plus:SI (reg:SI %eax [152]) (const_int 40 [0x28])) [14 .to+0 S4 A32])) 38 {*movsi_1} (insn_list 233 (nil)) (expr_list:REG_DEAD (reg:SI %eax [152]) (nil))) (insn 648 235 238 13 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 238 648 239 13 (set (reg:HI %ax [orig:155 .DbId ] [155]) (mem/s:HI (plus:SI (reg:SI %edx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32])) 42 {*movhi_1} (insn_list 648 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (expr_list:REG_EQUIV (mem/s:HI (plus:SI (reg:SI %edx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32]) (nil)))) (insn:HI 239 238 241 13 (set (mem/s:HI (plus:SI (reg/f:SI %ebp) (const_int -28 [0xffffffe4])) [13 ToTkn.DbId+0 S2 A32]) (reg:HI %ax [orig:155 .DbId ] [155])) 42 {*movhi_1} (insn_list 238 (nil)) (expr_list:REG_DEAD (reg:HI %ax [orig:155 .DbId ] [155]) (nil))) (note:HI 241 239 717 13 NOTE_INSN_DELETED) (insn 717 241 718 13 (set (reg:SI %eax) (mem/f:SI (symbol_ref:SI ("ClassBug") [flags 0x40] ) [2 ClassBug+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 718 717 243 13 (set (reg:CCNO %eflags) (compare:CCNO (reg:SI %eax) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (jump_insn:HI 243 718 286 13 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 762) (pc))) 366 {*jcc_1} (insn_list 242 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 13, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 15, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 286 243 555 15 271 "" [2 uses]) (note:HI 555 286 288 15 [bb 15] NOTE_INSN_BASIC_BLOCK) (insn:HI 288 555 289 15 (set (reg:CCZ %eflags) (compare:CCZ (reg/v:SI %ebx [orig:110 ToPart ] [110]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (nil)) (jump_insn:HI 289 288 703 15 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 763) (pc))) 366 {*jcc_1} (insn_list 288 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 15, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 16, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 703 289 701 16 295 "" [3 uses]) (note 701 703 660 16 [bb 16] NOTE_INSN_BASIC_BLOCK) (insn 660 701 393 16 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 393 660 466 16 (set (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 660 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) ;; End of basic block 16, registers live: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 17, registers live: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 466 393 577 17 274 "" [1 uses]) (note:HI 577 466 468 17 [bb 17] NOTE_INSN_BASIC_BLOCK) (insn:HI 468 577 613 17 (parallel [ (set (reg/v:SI %esi [orig:111 j ] [111]) (plus:SI (reg/v:SI %esi [orig:111 j ] [111]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn:HI 613 468 600 17 (parallel [ (set (reg:SI %edi [187]) (plus:SI (reg:SI %edi [187]) (const_int 20 [0x14]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (note:HI 600 613 471 17 NOTE_INSN_LOOP_VTOP) (insn:HI 471 600 472 17 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (nil)) (insn:HI 472 471 473 17 (set (reg/s:QI %dl [175]) (eq:QI (reg:CCZ %eflags) (const_int 0 [0x0]))) 362 {*setcc_1} (insn_list 471 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_EQUAL (eq:QI (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0])) (nil)))) (insn:HI 473 472 474 17 (set (reg:CC %eflags) (compare:CC (reg/v:SI %esi [orig:111 j ] [111]) (const_int 2 [0x2]))) 2 {*cmpsi_1_insn} (insn_list 468 (nil)) (nil)) (insn:HI 474 473 475 17 (set (reg/s:QI %al [177]) (leu:QI (reg:CC %eflags) (const_int 0 [0x0]))) 362 {*setcc_1} (insn_list 473 (nil)) (expr_list:REG_DEAD (reg:CC %eflags) (expr_list:REG_EQUAL (leu:QI (reg/v:SI %esi [orig:111 j ] [111]) (const_int 2 [0x2])) (nil)))) (note:HI 475 474 476 17 NOTE_INSN_DELETED) (insn:HI 476 475 477 17 (set (reg:CCZ %eflags) (compare:CCZ (and:QI (reg/s:QI %dl [175]) (reg/s:QI %al [177])) (const_int 0 [0x0]))) 208 {*testqi_1} (insn_list 472 (insn_list 474 (nil))) (expr_list:REG_DEAD (reg/s:QI %dl [175]) (expr_list:REG_DEAD (reg/s:QI %al [177]) (nil)))) (jump_insn:HI 477 476 589 17 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 481) (pc))) 366 {*jcc_1} (insn_list 476 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 1100 [0x44c]) (nil)))) ;; End of basic block 17, registers live: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 589 477 738 NOTE_INSN_LOOP_END) ;; Start of basic block 18, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note 738 589 728 18 [bb 18] NOTE_INSN_BASIC_BLOCK) (insn 728 738 729 18 (parallel [ (set (mem/f:SI (symbol_ref:SI ("PartCount") [flags 0x40] ) [14 PartCount+0 S4 A32]) (plus:SI (mem/f:SI (symbol_ref:SI ("PartCount") [flags 0x40] ) [14 PartCount+0 S4 A32]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn 729 728 730 18 (set (reg:SI %eax [152]) (reg:SI %edi [187])) 38 {*movsi_1} (nil) (nil)) (insn 730 729 731 18 (parallel [ (set (reg:SI %eax [152]) (plus:SI (reg:SI %eax [152]) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) [23 S4 A32]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn 731 730 732 18 (set (reg/v:SI %ebx [orig:110 ToPart ] [110]) (mem/s:SI (plus:SI (reg:SI %eax [152]) (const_int 40 [0x28])) [14 .to+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_DEAD (reg:SI %eax [152]) (nil))) (insn 732 731 733 18 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 733 732 734 18 (set (reg:HI %ax [orig:155 .DbId ] [155]) (mem/s:HI (plus:SI (reg:SI %edx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32])) 42 {*movhi_1} (nil) (expr_list:REG_EQUIV (mem/s:HI (plus:SI (reg:SI %edx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32]) (expr_list:REG_DEAD (reg:SI %edx) (nil)))) (insn 734 733 735 18 (set (mem/s:HI (plus:SI (reg/f:SI %ebp) (const_int -28 [0xffffffe4])) [13 ToTkn.DbId+0 S2 A32]) (reg:HI %ax [orig:155 .DbId ] [155])) 42 {*movhi_1} (nil) (expr_list:REG_DEAD (reg:HI %ax [orig:155 .DbId ] [155]) (nil))) (insn 735 734 736 18 (set (reg:SI %eax) (mem/f:SI (symbol_ref:SI ("ClassBug") [flags 0x40] ) [2 ClassBug+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 736 735 737 18 (set (reg:CCNO %eflags) (compare:CCNO (reg:SI %eax) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (jump_insn 737 736 762 18 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 286) (pc))) 366 {*jcc_1} (nil) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (expr_list:REG_DEAD (reg:CCZ %eflags) (nil)))) ;; End of basic block 18, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 19, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 762 737 551 19 300 "" [1 uses]) (note:HI 551 762 259 19 [bb 19] NOTE_INSN_BASIC_BLOCK) (insn:HI 259 551 649 19 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (reg/v:SI %ebx [orig:110 ToPart ] [110])) 38 {*movsi_1} (nil) (nil)) (insn 649 259 260 19 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 260 649 668 19 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 649 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (insn 668 260 262 19 (set (reg:SI %eax [159]) (plus:SI (reg/v:SI %esi [orig:111 j ] [111]) (const_int 1 [0x1]))) 150 {*lea_1} (nil) (nil)) (insn:HI 262 668 263 19 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg:SI %eax [159])) 38 {*movsi_1} (insn_list 668 (nil)) (expr_list:REG_DEAD (reg:SI %eax [159]) (nil))) (insn:HI 263 262 264 19 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref/f:SI ("*.LC25") [flags 0x2] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 264 263 265 19 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 265 264 269 19 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("sprintf") [flags 0x41] ) [0 S1 A8]) (const_int 20 [0x14]))) 531 {*call_value_0} (nil) (expr_list:REG_EH_REGION (const_int 0 [0x0]) (nil)) (nil)) (insn:HI 269 265 270 19 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %eax [158]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 265 (nil)) (expr_list:REG_DEAD (reg:SI %eax [158]) (nil))) (jump_insn:HI 270 269 553 19 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 286) (pc))) 366 {*jcc_1} (insn_list 269 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (nil)))) ;; End of basic block 19, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 20, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 553 270 281 20 [bb 20] NOTE_INSN_BASIC_BLOCK) (insn:HI 281 553 282 20 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 282 281 283 20 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 283 282 742 20 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Ut_TraceMsg") [flags 0x41] ) [0 S1 A8]) (const_int 8 [0x8]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (insn 742 283 743 20 (set (reg:CCZ %eflags) (compare:CCZ (reg/v:SI %ebx [orig:110 ToPart ] [110]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (nil)) (jump_insn 743 742 763 20 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 703) (pc))) 366 {*jcc_1} (nil) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (expr_list:REG_DEAD (reg:CCZ %eflags) (nil)))) ;; End of basic block 20, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 22, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 763 743 558 22 301 "" [1 uses]) (note:HI 558 763 651 22 [bb 22] NOTE_INSN_BASIC_BLOCK) (insn 651 558 308 22 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 308 651 309 22 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 651 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 309 308 310 22 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 310 309 652 22 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 652 310 311 22 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 311 652 312 22 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 652 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 312 311 315 22 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Env_IsValidToken") [flags 0x41] ) [0 S1 A8]) (const_int 16 [0x10]))) 531 {*call_value_0} (nil) (nil) (nil)) (insn:HI 315 312 316 22 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %eax [orig:96 T.288 ] [96]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 312 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:96 T.288 ] [96]) (nil))) (jump_insn:HI 316 315 561 22 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 703) (pc))) 366 {*jcc_1} (insn_list 315 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (nil)))) ;; End of basic block 22, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 23, registers live: 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 561 316 326 23 [bb 23] NOTE_INSN_BASIC_BLOCK) (insn:HI 326 561 327 23 (set (reg/f:SI %eax [orig:97 PartToken.289 ] [97]) (plus:SI (reg/f:SI %ebp) (const_int -40 [0xffffffd8]))) 150 {*lea_1} (nil) (expr_list:REG_EQUIV (plus:SI (reg/f:SI %ebp) (const_int -40 [0xffffffd8])) (nil))) (insn:HI 327 326 654 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 24 [0x18])) [0 S4 A32]) (reg/f:SI %eax [orig:97 PartToken.289 ] [97])) 38 {*movsi_1} (insn_list 326 (nil)) (expr_list:REG_DEAD (reg/f:SI %eax [orig:97 PartToken.289 ] [97]) (nil))) (insn 654 327 328 23 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 328 654 329 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 20 [0x14])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 654 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 329 328 330 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 330 329 331 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 331 330 332 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg/v:SI %ebx [orig:110 ToPart ] [110])) 38 {*movsi_1} (nil) (expr_list:REG_DEAD (reg/v:SI %ebx [orig:110 ToPart ] [110]) (nil))) (insn:HI 332 331 333 23 (set (reg:SI %eax [orig:160 VpartsDir ] [160]) (mem/f:SI (symbol_ref:SI ("VpartsDir") [flags 0x40] ) [3 VpartsDir+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/f:SI (symbol_ref:SI ("VpartsDir") [flags 0x40] ) [3 VpartsDir+0 S4 A32]) (nil))) (insn:HI 333 332 655 23 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (reg:SI %eax [orig:160 VpartsDir ] [160])) 38 {*movsi_1} (insn_list 332 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:160 VpartsDir ] [160]) (nil))) (insn 655 333 334 23 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 334 655 335 23 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 655 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 335 334 337 23 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Grp_GetEntry") [flags 0x41] ) [0 S1 A8]) (const_int 28 [0x1c]))) 531 {*call_value_0} (nil) (nil) (nil)) (insn:HI 337 335 338 23 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %eax [orig:99 T.291 ] [99]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 335 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:99 T.291 ] [99]) (nil))) (jump_insn:HI 338 337 563 23 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 345) (pc))) 366 {*jcc_1} (insn_list 337 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 23, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 24, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 563 338 343 24 [bb 24] NOTE_INSN_BASIC_BLOCK) (insn:HI 343 563 344 24 (set (reg:SI %eax [orig:161 PartToken.Handle ] [161]) (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -40 [0xffffffd8])) [3 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -40 [0xffffffd8])) [3 S4 A32]) (nil))) (insn:HI 344 343 345 24 (set (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -32 [0xffffffe0])) [3 S4 A32]) (reg:SI %eax [orig:161 PartToken.Handle ] [161])) 38 {*movsi_1} (insn_list 343 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:161 PartToken.Handle ] [161]) (nil))) ;; End of basic block 24, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 25, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 345 344 564 25 279 "" [1 uses]) (note:HI 564 345 656 25 [bb 25] NOTE_INSN_BASIC_BLOCK) (insn 656 564 346 25 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 346 656 348 25 (set (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 656 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (insn:HI 348 346 349 25 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 346 (nil)) (nil)) (jump_insn:HI 349 348 566 25 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 466) (pc))) 366 {*jcc_1} (insn_list 348 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 25, registers live: 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 26, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 566 349 354 26 [bb 26] NOTE_INSN_BASIC_BLOCK) (note:HI 354 566 355 26 NOTE_INSN_DELETED) (insn:HI 355 354 356 26 (set (reg:SI %eax [orig:163 SeedHandle ] [163]) (mem/f:SI (symbol_ref:SI ("*SeedHandle.7") [flags 0x2] ) [3 SeedHandle+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/f:SI (symbol_ref:SI ("*SeedHandle.7") [flags 0x2] ) [3 SeedHandle+0 S4 A32]) (nil))) (insn:HI 356 355 357 26 (set (reg:CCZ %eflags) (compare:CCZ (mem/s:SI (plus:SI (reg/f:SI %ebp) (const_int -32 [0xffffffe0])) [3 S4 A32]) (reg:SI %eax [orig:163 SeedHandle ] [163]))) 2 {*cmpsi_1_insn} (insn_list 355 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:163 SeedHandle ] [163]) (nil))) (jump_insn:HI 357 356 568 26 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 396) (pc))) 366 {*jcc_1} (insn_list 356 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 500 [0x1f4]) (nil)))) ;; End of basic block 26, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 27, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 568 357 657 27 [bb 27] NOTE_INSN_BASIC_BLOCK) (insn 657 568 384 27 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 384 657 385 27 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 657 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 385 384 386 27 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 386 385 658 27 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 658 386 387 27 (set (reg:SI %eax [166]) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 387 658 388 27 (parallel [ (set (reg:SI %eax [166]) (plus:SI (reg:SI %eax [166]) (const_int 1 [0x1]))) (clobber (reg:CC %eflags)) ]) 154 {*addsi_1} (insn_list 658 (nil)) (expr_list:REG_UNUSED (reg:CC %eflags) (expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (nil)))) (insn:HI 388 387 659 27 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (reg:SI %eax [166])) 38 {*movsi_1} (insn_list 387 (nil)) (expr_list:REG_DEAD (reg:SI %eax [166]) (nil))) (insn 659 388 389 27 (set (reg:SI %ecx) (plus:SI (reg/f:SI %ebp) (const_int -32 [0xffffffe0]))) 150 {*lea_1} (nil) (nil)) (insn:HI 389 659 390 27 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 659 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 390 389 764 27 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Part_Traverse") [flags 0x3] ) [0 S1 A8]) (const_int 20 [0x14]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (jump_insn 764 390 765 27 (set (pc) (label_ref 703)) -1 (nil) (nil)) ;; End of basic block 27, registers live: 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 765 764 760) ;; Start of basic block 28, registers live: 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 760 765 584 28 298 "" [1 uses]) (note:HI 584 760 500 28 [bb 28] NOTE_INSN_BASIC_BLOCK) (insn:HI 500 584 666 28 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg:SI %ecx [orig:117 pretmp.492 ] [117])) 38 {*movsi_1} (nil) (expr_list:REG_DEAD (reg:SI %ecx [orig:117 pretmp.492 ] [117]) (nil))) (insn 666 500 501 28 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 20 [0x14])) [3 Z+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 501 666 667 28 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (reg:SI %eax)) 38 {*movsi_1} (insn_list 666 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (insn 667 501 502 28 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 16 [0x10])) [3 F+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 502 667 503 28 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 667 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (call_insn:HI 503 502 772 28 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Ut_PrintErr") [flags 0x41] ) [0 S1 A8]) (const_int 12 [0xc]))) 531 {*call_value_0} (nil) (nil) (nil)) ;; End of basic block 28, registers live: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 30, registers live: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 772 503 754 30 302 "" [1 uses]) (note 754 772 746 30 [bb 30] NOTE_INSN_BASIC_BLOCK) (insn 746 754 747 30 (set (mem/f:SI (symbol_ref:SI ("Test") [flags 0x40] ) [2 Test+0 S4 A32]) (reg:SI %eax [orig:105 iftmp.297 ] [105])) 38 {*movsi_1} (nil) (nil)) (insn 747 746 748 30 (use (reg/i:SI %eax [ ])) -1 (nil) (nil)) (insn 748 747 749 30 (parallel [ (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 60 [0x3c]))) (clobber (reg:CC %eflags)) (clobber (mem:BLK (scratch) [0 A8])) ]) 515 {*pro_epilogue_adjust_stack_1} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn 749 748 750 30 (parallel [ (set (reg:SI %ebx) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (nil) (nil)) (insn 750 749 751 30 (parallel [ (set (reg:SI %esi) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (nil) (nil)) (insn 751 750 752 30 (parallel [ (set (reg:SI %edi) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (nil) (nil)) (insn 752 751 753 30 (parallel [ (set (reg/f:SI %ebp) (mem:SI (reg/f:SI %esp) [0 S4 A8])) (set (reg/f:SI %esp) (plus:SI (reg/f:SI %esp) (const_int 4 [0x4]))) ]) 35 {popsi1} (nil) (nil)) (jump_insn 753 752 756 30 (return) 388 {return_internal} (nil) (nil)) ;; End of basic block 30, registers live: 0 [ax] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 756 753 761) ;; Start of basic block 31, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label 761 756 529 31 299 "" [1 uses]) (note:HI 529 761 72 31 [bb 31] NOTE_INSN_BASIC_BLOCK) (note:HI 72 529 723 31 NOTE_INSN_DELETED) (insn 723 72 724 31 (set (reg:SI %eax) (mem/f:SI (symbol_ref:SI ("ClassBug") [flags 0x40] ) [2 ClassBug+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn 724 723 74 31 (set (reg:CCNO %eflags) (compare:CCNO (reg:SI %eax) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (nil) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (jump_insn:HI 74 724 531 31 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 86) (pc))) 366 {*jcc_1} (insn_list 73 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 3000 [0xbb8]) (nil)))) ;; End of basic block 31, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 32, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 531 74 78 32 [bb 32] NOTE_INSN_BASIC_BLOCK) (insn:HI 78 531 79 32 (set (reg:SI %eax [orig:67 Traverses.259 ] [67]) (mem/f:SI (symbol_ref:SI ("*Traverses.8") [flags 0x2] ) [3 Traverses+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (note:HI 79 78 722 32 NOTE_INSN_DELETED) (insn 722 79 673 32 (parallel [ (set (reg:SI %edx [123]) (const_int 0 [0x0])) (clobber (reg:CC %eflags)) ]) 36 {*movsi_xor} (nil) (expr_list:REG_UNUSED (reg:CC %eflags) (nil))) (insn 673 722 82 32 (parallel [ (set (reg:SI %eax [124]) (udiv:SI (reg:SI %eax [orig:67 Traverses.259 ] [67]) (mem/f:SI (symbol_ref:SI ("QueBug") [flags 0x40] ) [3 QueBug+0 S4 A32]))) (set (reg:SI %edx [123]) (umod:SI (reg:SI %eax [orig:67 Traverses.259 ] [67]) (mem/f:SI (symbol_ref:SI ("QueBug") [flags 0x40] ) [3 QueBug+0 S4 A32]))) (use (reg:SI %edx [123])) (clobber (reg:CC %eflags)) ]) 204 {*udivmodsi4_noext} (insn_list 78 (insn_list 672 (nil))) (expr_list:REG_UNUSED (reg:SI %eax [124]) (expr_list:REG_UNUSED (reg:CC %eflags) (nil)))) (insn:HI 82 673 83 32 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %edx [123]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 673 (nil)) (expr_list:REG_DEAD (reg:SI %edx [123]) (nil))) (jump_insn:HI 83 82 86 32 (set (pc) (if_then_else (ne (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 130) (pc))) 366 {*jcc_1} (insn_list 82 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 5000 [0x1388]) (nil)))) ;; End of basic block 32, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 33, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 86 83 533 33 254 "" [1 uses]) (note:HI 533 86 634 33 [bb 33] NOTE_INSN_BASIC_BLOCK) (insn 634 533 88 33 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 88 634 635 33 (set (reg:SI %eax [orig:74 T.266 ] [74]) (zero_extend:SI (mem/s:HI (plus:SI (reg:SI %edx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32]))) 81 {*zero_extendhisi2_movzwl} (insn_list 634 (nil)) (nil)) (insn 635 88 101 33 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 101 635 102 33 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 635 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (insn:HI 102 101 103 33 (set (reg:SI %edx [orig:128 .Handle ] [128]) (mem/s:SI (reg:SI %edx [2]) [3 .Handle+0 S4 A32])) 38 {*movsi_1} (insn_list 636 (nil)) (expr_list:REG_EQUIV (mem/s:SI (reg:SI %ecx) [3 .Handle+0 S4 A32]) (nil))) (insn:HI 103 102 105 33 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %edx [orig:128 .Handle ] [128])) 38 {*movsi_1} (insn_list 102 (nil)) (expr_list:REG_DEAD (reg:SI %edx [orig:128 .Handle ] [128]) (nil))) (insn:HI 105 103 106 33 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg:SI %eax [orig:129 T.266 ] [129])) 38 {*movsi_1} (insn_list 88 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:129 T.266 ] [129]) (nil))) (insn:HI 106 105 107 33 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref/f:SI ("*.LC24") [flags 0x2] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 107 106 108 33 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 108 107 112 33 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("sprintf") [flags 0x41] ) [0 S1 A8]) (const_int 20 [0x14]))) 531 {*call_value_0} (nil) (expr_list:REG_EH_REGION (const_int 0 [0x0]) (nil)) (nil)) (insn:HI 112 108 113 33 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %eax [127]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 108 (nil)) (expr_list:REG_DEAD (reg:SI %eax [127]) (nil))) (jump_insn:HI 113 112 535 33 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 130) (pc))) 366 {*jcc_1} (insn_list 112 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (nil)))) ;; End of basic block 33, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 34, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 535 113 124 34 [bb 34] NOTE_INSN_BASIC_BLOCK) (insn:HI 124 535 125 34 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 125 124 126 34 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 126 125 766 34 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Ut_TraceMsg") [flags 0x41] ) [0 S1 A8]) (const_int 8 [0x8]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (jump_insn 766 126 767 34 (set (pc) (label_ref 130)) -1 (nil) (nil)) ;; End of basic block 34, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 767 766 182) ;; Start of basic block 35, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 182 767 545 35 264 "" [1 uses]) (note:HI 545 182 642 35 [bb 35] NOTE_INSN_BASIC_BLOCK) (insn 642 545 192 35 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 192 642 193 35 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 642 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn:HI 193 192 194 35 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 194 193 643 35 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 643 194 195 35 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 195 643 196 35 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 643 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn:HI 196 195 768 35 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("BMT_DeletePartDrawObj") [flags 0x41] ) [0 S1 A8]) (const_int 16 [0x10]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (jump_insn 768 196 769 35 (set (pc) (label_ref 695)) -1 (nil) (nil)) ;; End of basic block 35, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 769 768 202) ;; Start of basic block 36, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 202 769 546 36 262 "" [1 uses]) (note:HI 546 202 204 36 [bb 36] NOTE_INSN_BASIC_BLOCK) (insn:HI 204 546 645 36 (set (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) [23 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int -20 [0xffffffec])) [23 S4 A32]) (nil))) (insn 645 204 205 36 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 205 645 206 36 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 20 [0x14])) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 645 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (insn:HI 206 205 207 36 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn:HI 207 206 669 36 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (insn 669 207 209 36 (set (reg/f:SI %eax [142]) (plus:SI (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (const_int 16 [0x10]))) 150 {*lea_1} (insn_list 204 (nil)) (nil)) (insn:HI 209 669 210 36 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg/f:SI %eax [142])) 38 {*movsi_1} (insn_list 669 (nil)) (expr_list:REG_DEAD (reg/f:SI %eax [142]) (nil))) (insn:HI 210 209 211 36 (set (reg:SI %eax [orig:143 .yy ] [143]) (mem/s:SI (plus:SI (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (const_int 32 [0x20])) [14 .yy+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_EQUIV (mem/s:SI (plus:SI (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (const_int 32 [0x20])) [14 .yy+0 S4 A32]) (nil))) (insn:HI 211 210 212 36 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (reg:SI %eax [orig:143 .yy ] [143])) 38 {*movsi_1} (insn_list 210 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:143 .yy ] [143]) (nil))) (insn:HI 212 211 213 36 (set (reg:SI %eax [orig:144 .xx ] [144]) (mem/s:SI (plus:SI (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (const_int 28 [0x1c])) [14 .xx+0 S4 A32])) 38 {*movsi_1} (nil) (expr_list:REG_DEAD (reg/f:SI %edx [orig:83 PartObj.275 ] [83]) (expr_list:REG_EQUIV (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (nil)))) (insn:HI 213 212 214 36 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %eax [orig:144 .xx ] [144])) 38 {*movsi_1} (insn_list 212 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:144 .xx ] [144]) (nil))) (call_insn:HI 214 213 770 36 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("BMT_ExportPart") [flags 0x41] ) [0 S1 A8]) (const_int 24 [0x18]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (jump_insn 770 214 771 36 (set (pc) (label_ref 695)) -1 (nil) (nil)) ;; End of basic block 36, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 771 770 396) ;; Start of basic block 37, registers live: 6 [bp] 7 [sp] 16 [argp] 20 [frame] (code_label:HI 396 771 569 37 283 "" [1 uses]) (note:HI 569 396 661 37 [bb 37] NOTE_INSN_BASIC_BLOCK) (insn 661 569 410 37 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 12 [0xc])) [14 Level+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 410 661 662 37 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 16 [0x10])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 661 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn 662 410 411 37 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 8 [0x8])) [26 PartTkn+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 411 662 412 37 (set (reg:SI %eax [orig:170 .Handle ] [170]) (mem/s:SI (reg:SI %ecx) [3 .Handle+0 S4 A32])) 38 {*movsi_1} (insn_list 662 (nil)) (expr_list:REG_EQUIV (mem/s:SI (reg:SI %ecx) [3 .Handle+0 S4 A32]) (nil))) (insn:HI 412 411 413 37 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 12 [0xc])) [0 S4 A32]) (reg:SI %eax [orig:170 .Handle ] [170])) 38 {*movsi_1} (insn_list 411 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:170 .Handle ] [170]) (nil))) (note:HI 413 412 414 37 NOTE_INSN_DELETED) (insn:HI 414 413 415 37 (set (reg:SI %eax [orig:171 .DbId ] [171]) (zero_extend:SI (mem/s:HI (plus:SI (reg:SI %ecx) (const_int 4 [0x4])) [13 .DbId+0 S2 A32]))) 81 {*zero_extendhisi2_movzwl} (nil) (expr_list:REG_DEAD (reg:SI %ecx) (expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (nil)))) (insn:HI 415 414 416 37 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg:SI %eax [orig:171 .DbId ] [171])) 38 {*movsi_1} (insn_list 414 (nil)) (expr_list:REG_DEAD (reg:SI %eax [orig:171 .DbId ] [171]) (nil))) (insn:HI 416 415 417 37 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref/f:SI ("*.LC26") [flags 0x2] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 417 416 418 37 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 418 417 427 37 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("sprintf") [flags 0x41] ) [0 S1 A8]) (const_int 20 [0x14]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (expr_list:REG_EH_REGION (const_int 0 [0x0]) (nil))) (nil)) (insn:HI 427 418 428 37 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (symbol_ref:SI ("Msg") [flags 0x40] )) 38 {*movsi_1} (nil) (nil)) (insn:HI 428 427 429 37 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (const_int 0 [0x0])) 38 {*movsi_1} (nil) (nil)) (call_insn:HI 429 428 663 37 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Ut_TraceMsg") [flags 0x41] ) [0 S1 A8]) (const_int 8 [0x8]))) 531 {*call_value_0} (nil) (expr_list:REG_UNUSED (reg:SI %eax) (nil)) (nil)) (insn 663 429 432 37 (set (reg:SI %eax) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 24 [0x18])) [4 Status+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 432 663 438 37 (set (reg:SI %edx [orig:77 T.269 ] [77]) (mem:SI (reg:SI %eax) [3 S4 A32])) 38 {*movsi_1} (insn_list 663 (nil)) (expr_list:REG_DEAD (reg:SI %eax) (nil))) (insn:HI 438 432 433 37 (set (reg:SI %eax [orig:104 iftmp.296 ] [104]) (const_int 1 [0x1])) 38 {*movsi_1} (nil) (nil)) (insn:HI 433 438 434 37 (set (reg:CCZ %eflags) (compare:CCZ (reg:SI %edx [orig:77 T.269 ] [77]) (const_int 0 [0x0]))) 0 {*cmpsi_ccno_1} (insn_list 432 (nil)) (nil)) (jump_insn:HI 434 433 572 37 (set (pc) (if_then_else (eq (reg:CCZ %eflags) (const_int 0 [0x0])) (label_ref 508) (pc))) 366 {*jcc_1} (insn_list 433 (nil)) (expr_list:REG_DEAD (reg:CCZ %eflags) (expr_list:REG_BR_PROB (const_int 7000 [0x1b58]) (nil)))) ;; End of basic block 37, registers live: 0 [ax] 1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; Start of basic block 38, registers live: 1 [dx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (note:HI 572 434 450 38 [bb 38] NOTE_INSN_BASIC_BLOCK) (insn:HI 450 572 664 38 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 8 [0x8])) [0 S4 A32]) (reg:SI %edx [orig:77 T.269 ] [77])) 38 {*movsi_1} (nil) (expr_list:REG_DEAD (reg:SI %edx [orig:77 T.269 ] [77]) (nil))) (insn 664 450 451 38 (set (reg:SI %edx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 20 [0x14])) [3 Z+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 451 664 665 38 (set (mem/f:SI (plus:SI (reg/f:SI %esp) (const_int 4 [0x4])) [0 S4 A32]) (reg:SI %edx)) 38 {*movsi_1} (insn_list 664 (nil)) (expr_list:REG_DEAD (reg:SI %edx) (nil))) (insn 665 451 452 38 (set (reg:SI %ecx) (mem/f:SI (plus:SI (reg/f:SI %ebp) (const_int 16 [0x10])) [3 F+0 S4 A32])) 38 {*movsi_1} (nil) (nil)) (insn:HI 452 665 758 38 (set (mem/f:SI (reg/f:SI %esp) [0 S4 A32]) (reg:SI %ecx)) 38 {*movsi_1} (insn_list 665 (nil)) (expr_list:REG_DEAD (reg:SI %ecx) (nil))) (call_insn 758 452 773 38 (set (reg:SI %eax) (call (mem:QI (symbol_ref:SI ("Ut_PrintErr") [flags 0x41] ) [0 S1 A8]) (const_int 12 [0xc]))) 531 {*call_value_0} (nil) (nil) (nil)) (jump_insn 773 758 774 38 (set (pc) (label_ref 772)) -1 (nil) (nil)) ;; End of basic block 38, registers live: 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] (barrier 774 773 628) (note 628 774 0 NOTE_INSN_DELETED)