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Volatiles and speculative memory access reordering...
- From: <aspiesrule at mcleodusa dot net>
- To: <gcc at gcc dot gnu dot org>
- Date: Thu, 27 Nov 2003 23:16:57 -0000
- Subject: Volatiles and speculative memory access reordering...
On modern CPU's such as Intel's Pentium 4 and Itanium 2, the CPU may reorder
accesses to volatiles across sequence points if a serializing insn is not
inserted at the sequence point. What should be done about this? On the
i386 with SSE2, we can use the "mfence" insn to serialize memory accesses.
But, how would we represent this in RTL? What should we do on platforms
that do not have dedicated serializing insns?
Lucas