Re: problem with subregs.

["Tal Agmon" <Tal dot Agmon at nsc dot com>]

Jim Wilson wrote:
>You probably have to fix the addhi3/subhi3 patterns to use special
>predicates that reject virtual registers, and SP/FP/AP in any sub-word
>mode.  Then the middle end will force a copy from a virtual reg to a
>pseudo reg before the subhi3 insn, and virtual register instantiation
>will happen in a move instruction where it should be successful.  This
>may take some tweaking to figure out how to get it right though.

Thank you, I manage to solve this problem with the virtuals. But it
seems that the main problem is still unsolved: I have a test with
multiply operations (mulsi that the compiler breaks to "mulhi"s).
I saw in one of the mulhi* insns a change in the mode of long (SI)
reg to HImode. In the compilation stages before reload, the insn's
predicates cannot prevent this since the registers are still pseudos.
After that it performs a wrong reload:

Reload 1: reload_in (HI) = (subreg:HI (reg/v:SI 14 ra [24]) 2)
                                                   -> ra is long

and then it will generate wrong code, or crash if the mul insn has an
updated predicates and constraints.

Do you have any idea why it's still reload this register? Could it be
impossible since the long registers in our architecture are in the
higher numbers?

Regards,

  Tal.