Re: inline asm constraints for conditions

[Gabriel Paubert <paubert at iram dot es>]

On Fri, Sep 26, 2003 at 01:39:35PM -0700, Richard Henderson wrote:
> On Fri, Sep 26, 2003 at 07:07:12PM +0100, David Howells wrote:
> > Would it be possible to get a new type of inline asm constraint added, such
> > that a "condition" can be an output?
> 
> Not like this, no.
> 
> The most basic problem for x86 is that the flags register dies too often.

Indeed.

> If we were to add the ability for it to live longer and be reloaded (say
> with lahf/sahf), then generic parts of the compiler would start trying to
> make use of it, which would almost certainly result in worse code overall
> even when the feature was not in use.

Furthermore lahf/sahf won't work since the overflow flag (used
for signed compares) is in another byte of the flags. According
to my docs, AMD has decided to remove these instructions in
64 bit mode (I don't have the hardware to test).

This would leave pushf/popf as the only way of moving flags
and it has some potentially dangerous side effects, especially
for kernel code (modifying interrupt mask to start with). 

Ok, that was my nitpicking of the day :-)

> For ia64, this ought to be possible.  On ia64 you'd use a constraint
> of "=c", which would imply the pair (pN,pN+1) for N even.  The one
> missing piece is that there is no language-level access to a BImode
> type.  Something that I've been meaning to try for a while is to 
> arrange for "bool" to have BImode and see what happens...
>

Any idea for PPC?

Each condition register is a 4-bit field, looks like PSImode, but some
instructions (CR logical) treat them as individual 1 bit fields, where 
BImode would seem optimal.

	Regards,
	Gabriel