This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
RE: Optimising redundant compares
- From: "Jon Beniston" <jbeniston at compxs dot com>
- To: "'Nathan Sidwell'" <nathan at codesourcery dot com>
- Cc: <gcc at gcc dot gnu dot org>
- Date: Thu, 25 Sep 2003 18:56:33 +0100
- Subject: RE: Optimising redundant compares
- Organization: CompXs
- Reply-to: <jbeniston at compxs dot com>
Hi Nathan,
> IIRC powerpc has something like this. To gcc, the compare
> instruction generates a set of bits indicating =, <, > etc,
> and the branch instructions select particular patterns. Have
> you looked there?
Yep, my port is very similar. The only apparent significant difference
is that I was using a fixed hard register, where as I believe the PPC
allows CC regs to be pseduos. I have tried to modify my code to work in
a similar way, but have stumbled across a problem with reloading as the
architecture I'm porting to is 16-bit. The problem is that the size of
MODE_CC is defined as 32-bits in machmode.def and I only have one 16-bit
register in my CC_REG class. The reloader therefore falls over when
trying to allocate 2 registers from CC_REG.
How would I go about modifying the size of MODE_CC in a portable way?
Will this cause any other problems? Should I add a second dummy register
in my CC_REG class? All suggestions greatly received.
Cheers,
Jon