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Re: ideas for modeling pipeline with bypass registers?
- From: <tm_gccmail at mail dot kloo dot net>
- To: Greg McGary <greg at mcgary dot org>
- Cc: gcc at gcc dot gnu dot org
- Date: Mon, 28 Jul 2003 16:19:08 -0700 (PDT)
- Subject: Re: ideas for modeling pipeline with bypass registers?
On 28 Jul 2003, Greg McGary wrote:
> I'm working on a GCC port to a pipelined machine that has 1 insn
> latency between ALU operation and numbered-register writeback
> (i.e., insn-0: ALU op
> insn-1: ...
> insn-2: ALU op result appears in destination register
>
> In order to make ALU ops available with no latency, there's a special
> "bypass" register that can be used before the register-file writeback.
> This bypass value is available for only one cycle, after which it is
> clobbered by the next ALU op.
I'm assuming this bypass register is an architecturally visible register?
Toshi