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Re: GCC for 8051 based architectures
- From: <tm_gccmail at mail dot kloo dot net>
- To: Julia Nilsson <juliahansnillson at yahoo dot ca>
- Cc: Shaun Jackman <sjackman at pathwayconnect dot com>, gcc at gcc dot gnu dot org
- Date: Tue, 15 Jul 2003 12:27:30 -0700 (PDT)
- Subject: Re: GCC for 8051 based architectures
On Tue, 15 Jul 2003, Julia Nilsson wrote:
>
> --- tm_gccmail@mail.kloo.net wrote:
> >
> > Yes, the 8051 instruction set was not really
> > designed for
> > compiler-generated code. It was designed in an era
> > when hand
> > assembly was more common.
> >
> Thats true but commercial compilers do exist for
> microcontrollers. What can be the possible issues with
> GCC for such a target?
> >
> > Most compiler optimizations require a reasonable
> > number of registers to
> > work efficiently, so even if the optimizations are
> > supported, they
> > may not work well on the 8051 anyway.
> >
> Thats OK but do you feel that if I have say an 8051
> based core with 16 GPRs then GCC will have lot many
> optimizations.
>
> GCC is supported for H8 that does not
> have that many registers but it has addressing modes
> and Memory Map that is more like we have in RISC.
I briefly looked at the 8051 ISA and there's two characteristics which may
cause serious problems in implementation:
1. The accumulator. GCC doesn't deal well with special registers.
2. The lack of offset addressing modes.
I didn't realize the 8051 had 8 GPRs...that's probably enough.
Toshi