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Re: Pre_dec and Post_inc insns
- From: <tm_gccmail at mail dot kloo dot net>
- To: Hans-Peter Nilsson <hp at bitrange dot com>
- Cc: Natasha Wilson <nat_w at operamail dot com>, gcc at gcc dot gnu dot org
- Date: Wed, 9 Jul 2003 17:43:18 -0700 (PDT)
- Subject: Re: Pre_dec and Post_inc insns
On Wed, 9 Jul 2003, Hans-Peter Nilsson wrote:
> On Wed, 9 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> > The load latency usually is two, BTW. This is fairly typical for a
> > pipelined processor with 5 stages. The Pentium, the SH, many MIPS and
> > other processors have a load latency of two clocks.
>
> But one I'm working on only has a one cycle load latency...
>
> Nevertheless, I hope you get my point that the usefulness of
> generating autoincdec before sched1 is a highly target-dependent
> detail, and that forcing one way or the other by making
> assumptions on universal latency figures would be bad.
>
> brgds, H-P
No, you're missing my point, I think.
The instruction scheduler should have maximum freedom to reorder
instructions, which means pre/post increment/decrement addressing modes
should be generated after sched1.
For your processor with a load latency of one clock, the instruction
scheduler should not reorder the load instructions so the natural
postincrements should be generated. If this is not happening, then this is
a problem with the machine description or the scheduler.
If this problem is "solved" by generating pre/post dec/inc before sched1,
then you are merely fixing the symptom and not the root problem. So, I
stand by my assertion that pre/post inc/dec should be generated after
sched1.
Toshi