register classes, predicates, constraints...

["Alexander Aganichev" <aaganichev at yandex dot ru>]

Hi!

I need to pass a register pair to the instruction pattern. Until
now everything worked just fine, but now I have created more
complex example and received "insn does not satisfy it's
constraints".

I have:
1) "e" register with REGNO 4, and "d" register with REGNO 5.
2) WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN set to 0.
3) register class DE_REGS which combines "d" and "e" registers.
4) HARD_REGNO_MODE_OK which returns true for "e" register and
   false for "d" register for HImode.
5) REG_CLASS_FROM_LETTER which returns DE_REGS class for "d"
   constraint.
6) HARD_REGNO_NREGS which returns 2 for "e" register in HImode.
7) the addhi3 instruction defined as follows:
(define_insn "addhi3"
  [(set (match_operand:HI 0 "z80_h_reg_dst_operand"
         "=S,     S,h,   x,   y,   d,wS,d,h*xy,h*xy, S")
        (plus:HI (match_operand:HI 1 "z80_h_reg_dst_operand"
         "%0,     0,0,   0,   0,   0,0, h,0,   bdS,  0")
                 (match_operand:HI 2 "z80_h_src_operand"
         " J,     K,bdhS,bdxS,bdyS,h,I, d,ui,  bdSui,h*xy")))
   (clobber (match_scratch:HI 3
         "=bdh*xy,X,X,   X,   X,   X,X, 1,bd,  X,    2"))]
  ""
  ...
8) z80_h_reg_dst_operand and z80_h_src_operand which refuse
   "e" register.
9) And, finally, the following complaint:
$ gcc/xgcc -Bgcc -s -S z80-test/test.c -o z80-test/test.s -O2
z80-test/test.c: In function `z1':
z80-test/test.c:83: error: insn does not satisfy its constraints:
(insn 16 15 17 1 0xdd3db0 (parallel [
            (set (reg/s:HI 2 l [22])
                (plus:HI (reg:HI 5 d)
                    (const_int 20 [0x14])))
            (clobber (scratch:HI))
        ]) 15 {addhi3} (insn_list 14 (nil))
    (nil))
z80-test/test.c:83: internal compiler error: in reload_cse_simplify_operands, at
 reload1.c:8343
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.

I do not expect the "d" register in HImode to be as operand 1 for
addhi3. Is it still be my fault or that's more likely a bug in register
allocator?

--
Alexander Aganichev

url: http://aaganichev.narod.ru
e-mail: aaganichev@yandex.ru
gsm: +7-095-786-1339